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Electrical Engineering homework help

ITCE272/340 Course Project:

A simple project done by yourself on MATLAB will get better mark than a copied advanced

project.

For example, use Laplace to analyze the Transfer Function and plot the Frequency Response

of one of the following filters:

Band Pass and Band Stop (Notch) Filter | Circuit | Theory – Electrical Academia

Electrical Engineering homework help

Scope:
When working in the laboratory an Engineer or Scientist records day-to-day progress in a logbook.

Once the experiment or series of experiments is complete however, a Formal Report for publication

is produced. For Engineers and Scientists, communicating their results is as important as getting

them in the first place because most of the work they do involves collaboration with other people.

Writing reports is an important skill for you to develop to help you during your degree, and later in

the workplace.

Requirements
You are required to submit 2 Formal Laboratory Reports, one on each of the due dates shown above.

Report 1: You can choose any experiment conducted in Semester 1

Report 2: From Semester 2 AND your experiment must relate to a different module to the one you

chose for the first report.

All reports must be typed; graphs and figures should be produced electronically.

Submission
All reports should be submitted electronically via Blackboard. The appropriate link and instructions

for doing this can be found in the ‘Coursework’ folder on Blackboard.

You must submit your report by 12:00 noon on the due date. If you are unable to complete the

work on time due to illness or severe problems, you must ask the Student Office for an extension

before the due date. Reports submitted after the due date and time will be subject to the standard

late penalties. Information about late submission penalties can be found in the ‘Coursework’ folder

on Blackboard. Reports submitted after 12:00 noon on the due date will count as 1 day late. Please

note that it is your responsibility to keep back-up copies of your work as necessary. Computer failure

and corrupt disks are not allowable excuses for deadline extension.

Format
The format of a formal laboratory report is almost standard throughout the world. The titles of the

sections may vary a little, but the required content does not. You can find an abundance of websites

that will give you tips on how to write a report. By searching for articles on the internet related to

‘writing lab reports and scientific papers’ you will find much information on the topic. The Formal

Report is typically made up of the following sections, although as mentioned above, each case may

vary slightly:

(i) Title

(ii) Abstract

(iii) Introduction (to include background information, context etc.)

(iv) Theory

(v) Methodology Materials, Methods and/or Description of Apparatus and/or Experimental

Procedure etc.

(vi) Results

(vii) Discussion

(viii) References

(ix) Appendices

You may also find useful guidance in:

Kircup, Les, (1994). “Experimental Method”, John Wiley & Sons, ISBN 0471335797, Hartley Library

catalogue number QC 39 KIR

Barrass, Robert, (1978). “Scientists must write”, Chapman & Hall, ISBN 0412154307, Hartley Library

catalogue number T11 BAR

Length
There is no fixed length for the report. It should be long enough to contain all the necessary

information and to make clear what you have done and what you have concluded. On the other

hand, it should be concise enough to contain no unnecessary or irrelevant information. As a general

guide about 6-10 pages in total is usually about right for a typical undergraduate experiment,

although this will clearly vary from experiment to experiment

Marking
The marking criteria will be the following:

Abstract 10% Write a summary of the report aimed at a non-
technical audience. This should briefly set out
the aims and objectives of the experiment
together with the outcome and conclusions.
Note that the emphasis is on writing in a style
that a lay person would be able to understand.

Marks are awarded based on a clear and
concise abstract in the appropriate tone. The
abstract clearly outlines the protocol, results
and conclusions made. Good use of English
language and grammar.

Introduction, Theory and Research 10% A well-presented introduction that has
reference to the practical along with reference
to existing research relevant to the practical
like reasons why this experiment may be
carried out in a research context. The theory
should be included and referenced.

It is also highly encouraged that the research
based around the theory of the experiment
should be explored to suggest how and why
this type of experiment and the fundamental
science behind it is needed in our modern-day
society.

Aims clearly indicated – these may be under an
additional subheading.

Marks are awarded based on the how well the
introduction is written in an appropriate tone
and uses good English language and grammar.
In-text citations have been with references
being from a variety of sources. For higher
marks the student has evaluated other
experiments that would allow you to reach the
same end point. The student will have also
considered errors and potential issues to look
out for when conducting this type of
experiment.

Methodology 10% The methodology should be clear and concise –
the methodology can be written either as a
series of bullet points or in prose. An
equipment list is present. Good use of English
language and grammar. The methodology
would allow a lay person to repeat the

experiment without hindrance. Risk
assessments delivered.

You should double check when writing this
section: Is it obvious what you have done? Are
things described in the right order? Does it
make sense? Is it written in an objective way? Is
it grammatically, correct? Has it been spell-
checked?

Results 30% Results are presented in a suitable format
(tables and graphs) Tables and graphs are
labelled. Any calculations used are clearly
explained and presented in a suitable format.
Any extrapolation of the results is clearly
highlighted.

Discussion and Conclusion 30% The results should clearly be reviewed and
analysed in the discussion section. Any
anomalies or trends have been highlighted and
the reason that particular outcome has
occurred discussed. Any potential error in the
experiment has been highlighted and an
explanation to how this error has been/could
be reduced is present. High marks are awarded
to the students who offer additional
information about the practical including way
to develop/improve the experiment if it was to
be carried out again.

Are all your conclusions justified by your
findings? Are the limitations of the experiment
explained? Are any improvements to the
experiment realistic? Is the error analysis
sufficient?

References, Quality of Report writing and
Structure 10%

References: In-text citations are present.
Appropriate references used. A reference
section at the end of the report exists and the
School of Engineering’s referencing system
used.

This includes the standard of the English
grammar and punctuation, the quality of
diagrams and the degree to which the report is
well structured, enabling a reader to
understand what you have done and why.

Is the information arranged into suitable
sections? Are the sections numbered and do
they have appropriate titles? Does each figure,

graph and table have a title? Does each figure,
graph, table, and equation have a number?

  • Scope:
  • Requirements
  • Submission
  • Format
  • Length
  • Marking

Electrical Engineering homework help

192 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Single-Stage High-Efficiency 48/1 V Sigma
Converter With Integrated Magnetics

Mohamed H. Ahmed , Student Member, IEEE, Chao Fei , Student Member, IEEE,
Fred C. Lee , Life Fellow, IEEE, and Qiang Li , Member, IEEE

Abstract—A high-efficiency, high-power-density Sigma
converter for a 48 V rack architecture in data centers is
proposed in this paper. The Sigma converter is a quasi-
parallel converter that uses a high-efficiency unregulated
converter to deliver the bulk power to the load. A small
buck converter is responsible for regulating the output volt-
age with prescribed dynamic responses. A design guideline
for Sigma converter with integrated magnetics is provided
in this paper. The unregulated converter is an LLC con-
verter designed with a printed circuit board (PCB) winding
matrix transformer, a structure which integrates four ele-
mental transformers into one core. The buck converter is
designed with discrete gallium nitride (GaN) devices and a
PCB winding inductor. The proposed Sigma converter op-
erates at 48 V input and 1 V-80 A output and can achieve a
power density of 420 W/in3 as well as a peak efficiency of
94%.

Index Terms—48 V voltage regulator module (VRM),
integrated magnetics, matrix transformer, Sigma converter.

I. INTRODUCTION

D UE TO the ever increasing load demands of data centersand telecommunication applications, a 10% share of the
total power consumption by 2020 [1] is predicted. These needs
are driving the power management solutions for increased
efficiency and power density. To fulfill digital content demands,
multicore processors with a greater number of cores and power-
hungry processors are increasing every year. With increasing
demands of high current (>220 A) at low voltage levels
(<1.85 V) for each CPU [2], the power consumption per server
rack is reaching 15 kW. This raises attention toward a more
efficient system architecture in the rack level. Traditionally,
data centers the system architecture as shown in Fig. 1(a) with
a 12 V bus backplane, thus, resulting in poor overall power
delivery efficiency due to the large distribution loss at the 12 V
bus. Shifting to higher bus voltages, 48 V instead of 12 V, was
proposed [3], and subsequently adopted, by Google as shown
in Fig. 1(b), where the uninterruptible power supply (UPS)

Manuscript received March 25, 2018; revised July 10, 2018, August
28, 2018, and November 15, 2018; accepted January 6, 2019. Date of
publication February 5, 2019; date of current version August 30, 2019.
(Corresponding authors: Mohamed H. Ahmed and Qiang Li.)

The authors are with the Center for Power Electronics Systems,
Virginia Polytechnic Institute and State University, Blacksburg, VA
24061 USA (e-mail:, mohamed4@vt.edu; feichao@vt.edu; fclee@vt.
edu; lqvt@vt.edu).

Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2019.2896082

Fig. 1. Data centers distribution system: (a) traditional ac distribution;
(b) dc distribution with 48 V bus.

systems are replaced by a local dc 48 V battery backup [4].
Significant challenges rise with that proposed architecture. The
48 V voltage regulator module (VRM) located in the vicinity
of the CPU has to be designed with very high efficiency and
high power density [5].

A great amount of work has been done with the 48 V VRM
for both data center and telecommunication applications. They
can be categorized as one-stage and two-stage solutions.

A two-stage 48 V VRM is the first commercially avail-
able solution by Vicor [3], [6]. Their soft-switched first-stage
buck-boost preregulator module (PRM), cascaded with a soft-
switched unregulated sine amplitude voltage transformation
module (VTM), enables their solution to achieve high efficiency
and high density. However, the solution is not easily scalable as
designed in high current levels (>100 A/module). Another two-
stage approach was used in [5], [7], and [8], with an unregulated
inductor-inductor-capacitor (LLC) dc–dc transformer (DCX) as
the first stage and a conventional multiphase regulated buck
converter for the second stage. This solution reported a high ef-
ficiency and high density with significant improvement for light
load efficiency. The two-stage architecture was proposed in [4]
and [9], replacing the isolated bus converters with a resonant
switched capacitor circuit that can achieve a high efficiency
of 98.2% and power density of 500 W/in2 for the first stage
converter; however, there is no reported two-stage efficiency or
power density for the 48/1 V conversion. Another state-of-art
product was proposed by STM Microelectronics [10] based on
a single-stage quasi-resonant converter with a current-doubler
rectifier reported in [11] and [12]. The converter can operate with
zero voltage switching (ZVS) in all loading conditions with a
high efficiency of 93%. However, the topology requires four
magnetic components, reducing the converter power density. In

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 193

Fig. 2. Sigma converter structure.

[13]–[15] a current-tripler 48 V VRM with a compact mag-
netic structure was proposed, together with a 1-MHz self-driven
scheme that solves the problem of synchronous rectifier (SR)
switching and can achieve very high efficiency at high-frequency
operation. However, in the proposed scheme not all the primary
side switches can achieve ZVS at light load, resulting in a sig-
nificant efficiency drop during light loading conditions.

The Sigma converter concept was first proposed in [16] and
[17], for 12 V VRMs that exhibited outstanding performance
over multiphase buck converters. The same architecture was
later used in different applications [18], [19] demonstrating a
very efficient operation. In this paper, the same concept was
revisited and proposed for a single-stage 48 V VRM [20]. The
Sigma converter is a quasi-parallel converter that connects two
converters in series from the input side, and in parallel from
the output side. One of the converters is an unregulated isolated
DCX that conducts the bulk power, while the other is a non-
isolated converter responsible for regulating the output voltage
(D2D), as shown in Fig. 2. A potential benefit of this architecture
is its ability to achieve higher conversion efficiency.

Further efforts should be made for the design of the DCX
and D2D to maximize the benefits of this power architecture.
The soft switching properties of the LLC converter enables
operation at a very high frequency to achieve high density while
achieving high efficiency, making it a suitable candidate for this
converter’s DCX. Integrating magnetics with PCB winding and
matrix transformer with the opportunity of flux cancellation has
been reported [21]–[27] to reduce the size and losses of the LLC
DCX transformer at high-frequency operation.

None of the preceding work has discussed the Sigma con-
verter design with integrated magnetics even though the matrix
transformer structure and design will impact the performance of
this converter significantly as will be discussed in the following
sections. In this paper, a detailed design guideline for the Sigma
converter with integrated magnetics will be discussed by which
the right matrix transformer structure can be chosen for differ-
ent input/output voltage variations to maximize the benefits of
this conversion system. A novel matrix transformer which inte-
grates four elemental transformers into one core structure with
printed circuit board (PCB) windings is proposed to achieve
high efficiency and power density. Accompanying the DCX is
a buck converter with PCB winding inductor to realize all the
stringent requirements for regulation dynamics while increasing
the power density.

TABLE I
PROPOSED CONVERTER SPECIFICATIONS AND LLC-DCX TURNS RATIO

DESIGN RANGE

This paper is organized as follows. Section II presents the
design principle of the Sigma converter architecture with inte-
grated magnetics. Section III discusses the optimal design of the
LLC-DCX with a PCB winding matrix transformer. Section IV
optimizes the design of the buck converter with a PCB wind-
ing inductor. Section V presents the converter prototype and the
experimental results. Section VI concludes this paper.

II. DESIGN GUIDELINE OF SIGMA CONVERTER WITH
INTEGRATED MAGNETICS

In the Sigma architecture, both converters have the same input
current, thus, the power sharing between them is proportional to
the input voltage across each of them as in (1). In the proposed
architecture, the DCX converter is an LLC converter operating
at resonant frequency, utilizing the matrix transformer’s leak-
age inductance to form the resonant tank with the addition of
resonant capacitor. The small leakage inductance of the matrix
transformer will result in a large Ln = Lm /Lr resulting in a
constant gain LLC converter that does not change much with
frequency variation. As a result, the input voltage of the DCX
will be the output voltage of the converter multiplied by the
DCX turns ratio n and the remaining voltage will appear on the
buck-D2D as given in (2). The DCX turns ratio n has a signifi-
cant role in the voltage distribution across these two converters
and consequently, the power sharing among them. For efficient
power conversion, the LLC-DCX is required to handle most of
the power as it can be designed with very high efficiency com-
pared to the buck-D2D; the condition VDCX � VD 2D should
be satisfied in order to achieve that goal.

The Sigma architecture has two main design constraints—
the first constraint is to achieve high efficiency of operation
by limiting the maximum allowable voltage appearing on the
buck converter during all operating conditions, this constraint
limits the minimum allowable turns ratio as given in (3). The
second constraint is to ensure a positive voltage across the buck
converter that is always higher than the maximum output voltage
by which the duty ratio is always (D < 1) and this condition
is given by (4) and sets the maximum allowable turns ratio.
Vinm in , Vinm ax , Vom in , Vom ax are the maximum and minimum
input and output voltages, respectively, Dm ax is the maximum
buck duty ratio, and Vbuckm ax is the maximum stress on the
buck converter.

Different applications will require a specific design of this
architecture based on the constraints mentioned above. The pro-
posed converter specifications and the turns ratio design range
are listed in Table I. The maximum allowable voltage across
the buck converter is set to be Vbuckm ax < 30 V , this will allow

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194 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 3. (a) Basic matrix transformer structure with multiple elemental
transformer. (b) Primary winding implementation with PCB winding.

using low voltage devices for the buck converter to maximize
its efficiency and maintain the bulk power to flow through the
LLC-DCX in all operating conditions

PDCX /PD 2D = VDCX /VD 2D (1)

VDCX = nVo VD 2D = Vin − nVo (2)

nm in >
Vinm ax − Vbuckm ax

Vom in
(3)

nm ax <
Vinm in
Vom ax

− 1
Dm ax

. (4)

Although the maximum turns ratio (nm ax = 43) will result in
the most efficient operation, the implementation of specific turns
ratio with matrix transformer is constrained by other limiting
factors. First, the matrix transformer with core simplification and
integration by the flux cancellation method has been proposed
in [21] and [25] by which two elemental transformers can be
integrated using a single UI-core, resulting in significant core
loss and footprint reduction. This means that we always need
an even number of elemental transformers (2, 4, 6, . . . , etc.)
in order to take the advantage of flux cancellation and core
integration for high efficiency and power density.

Second, the basic structure of matrix transformer with
multiple elemental transformers is shown in Fig. 3(a), where
the single transformer is divided into multiple elemental
transformers connected in series from the primary side and
in parallel from the output side. To ensure equal current
sharing between these elemental transformers, the number
of turns in each elemental transformer should be equal, i.e.,
(nTR1 = nTR2 = . . . = nTRN ). Third, with the requirement
of multiple turns per elemental transformer (nTRx > 1), these
turns should be implemented in more than one layer in order
to have an entrance and exit path for the primary side current
without using extra via or PCB layers as shown in Fig. 3(b).
Finally, the number of primary turns per PCB layer should be
equal in order to maintain a balanced magnetomotive force
(MMF) across the transformer winding and ensure perfectly
interleaved primary and secondary windings to reduce all
ac-related winding loss.

Applying these four PCB winding implementation related
constraints to the design specifications and architecture
constraints listed in Table I will result in all the design options

TABLE II
LLC-DCX WITH MATRIX TRANSFORMER OPTIONS FOR SIGMA CONVERTER

WITH DIFFERENT PRIMARY SIDE CONFIGURATIONS

Fig. 4. Proposed 48/1 V-80 A Sigma converter structure.

listed in Table II, where, NE is the number of elemental trans-
formers, nTR is the turns ratio of each elemental transformer,
and ntotal = NE × nTR is the LLC-DCX total transformer
ratio.

It is clear that different matrix transformer and primary side
configurations will have different impact on the Sigma converter
operation, the first and last options NE = 4 and NE = 10 will
result in the highest possible converter efficiency with the high-
est power flowing through the LLC-DCX. Although both have
the same impact on the architecture, for simplicity of the design,
the first option (NE = 4 )was chosen for this design, the case
with NE = 10 can be a possible candidate if a higher current
converter is required. Although half bridge (HB) configuration
have lower turns ratio, it requires more PCB layers compared to
the full bridge (FB) configuration to implement the PCB wind-
ing, so FB was selected to reduce the cost and complexity of the
proposed converter. The proposed Sigma converter structure is
shown in Fig. 4, the total DCX turns ratio is n = 40 : 1. The
benefits of this design can be shown from the power-sharing
graph in Fig. 5. At most operating conditions, the LLC-DCX
handles most of the output power by which higher overall ef-
ficiency is expected. The same design guidelines can be used
for other 48 V VRMs with different input and output voltage
and power requirements to select the optimal matrix transformer
structure for each application. The optimization of this matrix
transformer will be discussed in the following section to achieve
the highest possible efficiency and power density.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 195

Fig. 5. Power sharing between the LLC-DCX and the buck-D2D.

III. LLC CONVERTER WITH MATRIX TRANSFORMER DESIGN
AND OPTIMIZATION

The design of LLC-DCX for high output current and low
output voltages is very challenging. The necessity of paralleling
multiple SRs to handle this high output current results in cur-
rent sharing problems and large transformer termination losses,
a practice that should be avoided if possible. The concept of the
matrix transformer is to employ various elemental transformer
arrays interwired to form a single transformer. This will re-
duce the total transformer losses by splitting the current among
various elemental transformers and in the same time achiev-
ing flux cancellation wherever possible. The matrix transformer
has exhibited an outstanding performance when used in various
applications. In addition to minimizing termination losses, the
simple PCB winding implementation makes it suitable for this
application, where high output current of the LLC-DCX is re-
quired. In this section, the design and optimization of the matrix
transformer for the LLC-DCX will be discussed in detail.

A. Integration of LLC-DCX Matrix Transformer Structure
and PCB Winding Implementation

For the proposed Sigma converter, the LLC-DCX requires
a transformer with (40:1) turns ratio. This single transformer
was broken into four elemental transformer arrays as shown
in Fig. 6, where the transformer leakage and magnetizing in-
ductances with an additional capacitor are used to form the
resonant tank of the LLC-DCX. The primary windings of this
structure are connected in series while the secondary windings
are connected in parallel. Hence, there would be no current shar-
ing problem between paralleled secondary windings or SRs. To
further reduce conduction losses, the proposed structure par-
allels only two SRs at each secondary winding. Transformer
termination is the physical connection between the transformer
windings and the corresponding primary and secondary devices.
They contribute to a large portion of the transformer losses when
operating at high switching frequencies [21]. The matrix trans-
former structure helps split the output current among different
transformer outputs, thus reducing conduction and termination
losses significantly.

Fig. 6. Proposed LLC-DCX with matrix transformer.

A potential drawback of the matrix transformer approach is
the increased footprint and core loss due to the increased number
of magnetic cores. By operating at very high switching frequen-
cies, the magnetic core size can be reduced. To achieve high
power density, the complex four-transformer structure shown
must be simplified. Originally, the four elemental transformers
each utilize a separate UI-core as shown in Fig. 7(a). By rear-
ranging the four transformers in a way that two transformers
are on the top side (TR1 and TR2) and two on the bottom side
(TR3 and TR4) we can integrate the four transformers with one
core structure with a wide center leg as the return flux path of
each elemental transformer as in Fig. 7(b). By reversing the cur-
rent direction in TR3 and TR4, the flux in the wide center leg
will be in opposite directions and cancel each other, reducing
the total core loss and allowing the removal of this center leg
without scarifying any winding or core loss. Hence, the four
transformers can be integrated into one core structure with four
transformer pillars, which can be easily manufactured, saving a
significant amount of space and core loss as shown in Fig. 7(c).
The proposed integration method not only helps with the reduc-
tion of the core loss and footprint but also helps in achieving a
perfectly current sharing between all the transformer secondary
windings. Integrating the four transformers into a single core
structure helps achieve a symmetrical air gap for all the four el-
emental transformers. Although the four primary windings are
connected in series, each elemental transformer will see a differ-
ent magnetizing inductance determined by its own air gap; any
asymmetry in the magnetizing inductances between these ele-
mental transformers will create a current unbalance between the
secondary windings as well. With the single core structure, the
tolerance in these air gaps can be well-controlled to avoid these
problems when compared to using two single UI-cores [25].

The proposed matrix converter is implemented with a 14-layer
PCB and 2 oz copper for each layer. The detailed PCB winding
arrangement is shown in Fig. 8, the yellow arrows indicate the
current directions in the positive half-cycle. Layers 1 and 14 are

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196 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 7. Derivation of proposed matrix transformer: (a) original four ele-
mental transformer structure with separate UI-cores; (b) rearranged four
elemental transformers integrated in one core with a wide center leg;
and (c) integrated matrix transformers with one core structure without
center leg.

used to place the SRs and the output capacitors. Each set of paral-
lel SRs have one device on Layer 1 and the other device on Layer
14. These devices and capacitors are then connected to the cor-
responding secondary winding through vias. This arrangement
helps reduce the termination connections between windings and
SRs, while splitting the termination current into two layers. This
reduces termination losses significantly. Layers 3 and 6 are one
set of primary windings. In each layer, five turns are wrapped
around each core pillar and then both layers are connected in se-
ries, totaling the required 40 turns. A parallel connection is made
with Layers 9 and 12, which is another set of primary windings
to reduce conduction losses. The remaining layers are for the
center-tap secondary windings. Each layer has one turn, and all
layers are in parallel, to reduce conduction losses. The primary
and secondary windings are perfectly interleaved to reduce the
ac losses due to the proximity effect as shown in Fig. 8(b).

B. Matrix Transformer Design Optimization

To optimize the matrix transformer design, the tradeoff be-
tween total transformer losses and the footprint is evaluated, and
then the optimal switching frequency is selected. First, the im-

Fig. 8. PCB winding arrangement of the proposed matrix transformer:
(a) Layers 1&14 for SRs and output capacitors. (b) 14 layer PCB
arrangement. (c) Layers 3 and 9 for primary#1 windings. (d) Layers 6 and
12 for primary#2 windings. (e) Layers 2, 5, 8, and 11 for secondary#1
windings. (f) Layers 4, 7, 10, and 13 for secondary#2 windings.

TABLE III
CORE SHAPE IMPACT ON WINDING LOSS

pact of the core pillar shape on the winding losses was evaluated.
A rectangular core versus a circular core pillar was evaluated
by finite-element analysis (FEA) simulations; both cases have
the same core area and winding width. The results in Table III
show a 16–22% winding loss reduction with the circular post
due to the shorter current path length. Secondly, various high
frequency magnetic materials were previously surveyed in [5]
and the results showed that the ML-91 from Hitachi shows the
lowest core loss density for this high-frequency operation and
therefore, it was selected for the proposed LLC-DCX converter.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 197

Fig. 9. Transformer total losses and footprint at 1.5 MHz and full load.

Fig. 10. Transformer losses variation with switching frequency.
(a) Winding loss. (b) Core loss.

The design optimization of matrix transformer has been dis-
cussed in previous literature [23]–[25] for 400/12 V converters,
the total transformer loss is calculated at the optimal footprint
and then a design point is selected as a tradeoff between effi-
ciency and power density. The same design methodology was
used for this transformer by adding a new design parameter,
which is the operating switching frequency; the total trans-
former losses versus optimal footprint at full load and nominal
voltage conditions at 1.5 MHz switching frequency are shown
in Fig. 9. Due to the low output voltage and high frequency, the
volt·second applied on the core is very small, and the winding
losses are more dominant with very small core losses.

With lower switching frequencies, the ac related winding
loss will reduce, while the core loss increases due to the higher
volt·second as shown in Fig. 10. From the results in Fig. 11,
the total losses are highest at high switching frequencies, when
reducing the frequency, a reduction in the total losses occurs
until 1 MHz is reached. This is because the reduction in the
winding losses is counteracted by a significant increase in the
core losses, so further reducing the switching frequency will
result in a higher total transformer loss.

To achieve high efficiency and power density, the design re-
gion is highlighted in Fig. 11. The corresponding total loss vari-
ation with different switching frequencies was plotted as shown
in Fig. 12. With different footprints, the total losses tend to have
a minimum loss point at 1 MHz switching frequency; therefore,
1 MHz was selected as the operating frequency. The efficiency
of the converter was then calculated, and the final design point

Fig. 11. Transformer total loss versus footprint at different switching
frequencies.

Fig. 12. Transformer total losses versus switching frequency.

Fig. 13. Transformer fringing flux impact. (a) Cross-sectional view of
fringing flux distribution. (b) Current distribution in Layer 1. (c) Current
distribution in Layer 14.

was selected at a footprint of 300 mm2, since after that point,
the increase in the converter efficiency is marginal.

The magnetizing inductance of the transformer is created by
adding an air gap between the core pillar and the magnetic plate.
A great amount of fringing flux will spread through the air gap
creating many eddy current losses in the nearby layers. This
could be severe for the designed transformer. The fringing flux
at the air gap was simulated using ANSYS Maxwell and the
results shown in Fig. 13 show the strong fringing flux at the air
gap of one of the four elemental transformers. Layer 14, which
is closer to the air gap, handles the same amount of current,
but has ten times more losses than Layer 1. This is due to the

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198 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 14. Total transformer losses versus extending the core air gap.

TABLE IV
PARALLEL LAYER CURRENT DISTRIBUTION

strong fringing flux. To solve this issue, the air gap needs to
be pushed away from the PCB layers by a distance hf r . Using
FEA simulation, different hf r values were evaluated, and the
results are shown in Fig. 14. The total loss reduced significantly
with the higher hf r , until reaching a diminishing return point at
hf r = 0.6 mm, which was chosen in the final design.

In the proposed PCB winding arrangement shown in Fig. 8(b),
we have two primary parallel layers and four secondary winding
parallel layers. Although we minimized the losses due to the
fringing flux, it tends to attract the current to the layers close
to the transformer air gap resulting in an unbalanced current
sharing as listed in Table IV. This issue has not been addressed
in this paper and more analysis needs to be done in order to have
perfect current sharing between layers.

IV. BUCK CONVERTER DESIGN OPTIMIZATION WITH PCB
WINDING INDUCTOR

The Sigma converter was designed so that most of the power
flows through the higher efficiency LLC-DCX while the buck
converter is responsible for regulating the output voltage. From
Fig. 5, it is clear that the power and voltage applied to the buck
converter is variable, depending on the operating condition. In
the worst case (Vo = 0.8 V and Vin = 55 V), the buck con-
verter will experience a voltage stress of (Vbuckm ax = 23 V)
and should handle a current of about (33 A), so devices with a
minimum voltage rating of 40 V are required for the buck con-
verter. Low voltage gallium nitride (GaN) devices have shown
an outstanding performance compared with silicon devices. In
this design, the high side switch is EPC2015c while the low
voltage switch is EPC2024. An optimal layout presented in [28]
was used for the layout of the discrete GaN devices to minimize
the effect of parasitic inductances and their effect on switching
related losses. The inductor design for this buck converter is

Fig. 15. Proposed single-turn PCB winding inductor structure: (a) top
view and (b) cross sectional view.

Fig. 16. Measured efficiency of buck converter with discrete inductor
and PCB winding inductor.

important to achieve high power density and high efficiency.
For low voltage buck converters, the common practice is using
a commercial discrete inductor that has a very low dc resistance
(DCR) and low core loss. However, these inductors have a large
footprint and high profile, which reduces the overall converter
power density significantly.

In this proposed Sigma converter, the LLC-DCX uses a
14-layer PCB to implement the DCX transformer. The same
PCB can be utilized to implement a single-turn inductor. As the
PCB copper thickness is smaller than the copper foil thickness
used by discrete inductors, the inductor windings can be parallel
connected in multiple layers, to reduce the total inductor DCR.
The basic structure of the proposed PCB winding inductor is
shown in Fig. 15. An EI-core shape with ML-95 material from
Hitachi was used to implement the single-turn inductor. An in-
ductance of L = 190 nH and a DCR of RDC = 0.53 mΩ are
achieved. Although the DCR in the proposed design is larger
than the commercial discrete inductors, the efficiency reduc-
tion is negligible since the buck converter is only handling a
small amount of output current. Using this PCB winding induc-
tor will help achieve high power density without scarifying the
efficiency. A buck converter with commercial discrete inductor
and PCB winding inductor was experimentally evaluated. The
measured efficiency shown in Fig. 16 shows that the buck con-
verter with PCB winding inductor has higher efficiency in most
operating regions.

The reason for this is the lower core loss of the designed PCB
winding inductor; the ac-related loss of the PCB winding in-
ductor was evaluated using ANSYS Maxwell. The commercial
inductor used is from Würth Elektronik, and the ac-related loss
of this inductor was calculated based on the inductor loss cal-
culator software REDEXPERT. It can be shown from Table V
that the ac-related losses of the PCB winding inductor is three
times lower than that of the commercial inductor. These losses

Electrical Engineering homework help

ITCE272/340 Course Project:

A simple project done by yourself on MATLAB will get better mark than a copied advanced

project.

For example, use Laplace to analyze the Transfer Function and plot the Frequency Response

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Band Pass and Band Stop (Notch) Filter | Circuit | Theory – Electrical Academia

Electrical Engineering homework help

192 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Single-Stage High-Efficiency 48/1 V Sigma
Converter With Integrated Magnetics

Mohamed H. Ahmed , Student Member, IEEE, Chao Fei , Student Member, IEEE,
Fred C. Lee , Life Fellow, IEEE, and Qiang Li , Member, IEEE

Abstract—A high-efficiency, high-power-density Sigma
converter for a 48 V rack architecture in data centers is
proposed in this paper. The Sigma converter is a quasi-
parallel converter that uses a high-efficiency unregulated
converter to deliver the bulk power to the load. A small
buck converter is responsible for regulating the output volt-
age with prescribed dynamic responses. A design guideline
for Sigma converter with integrated magnetics is provided
in this paper. The unregulated converter is an LLC con-
verter designed with a printed circuit board (PCB) winding
matrix transformer, a structure which integrates four ele-
mental transformers into one core. The buck converter is
designed with discrete gallium nitride (GaN) devices and a
PCB winding inductor. The proposed Sigma converter op-
erates at 48 V input and 1 V-80 A output and can achieve a
power density of 420 W/in3 as well as a peak efficiency of
94%.

Index Terms—48 V voltage regulator module (VRM),
integrated magnetics, matrix transformer, Sigma converter.

I. INTRODUCTION

D UE TO the ever increasing load demands of data centersand telecommunication applications, a 10% share of the
total power consumption by 2020 [1] is predicted. These needs
are driving the power management solutions for increased
efficiency and power density. To fulfill digital content demands,
multicore processors with a greater number of cores and power-
hungry processors are increasing every year. With increasing
demands of high current (>220 A) at low voltage levels
(<1.85 V) for each CPU [2], the power consumption per server
rack is reaching 15 kW. This raises attention toward a more
efficient system architecture in the rack level. Traditionally,
data centers the system architecture as shown in Fig. 1(a) with
a 12 V bus backplane, thus, resulting in poor overall power
delivery efficiency due to the large distribution loss at the 12 V
bus. Shifting to higher bus voltages, 48 V instead of 12 V, was
proposed [3], and subsequently adopted, by Google as shown
in Fig. 1(b), where the uninterruptible power supply (UPS)

Manuscript received March 25, 2018; revised July 10, 2018, August
28, 2018, and November 15, 2018; accepted January 6, 2019. Date of
publication February 5, 2019; date of current version August 30, 2019.
(Corresponding authors: Mohamed H. Ahmed and Qiang Li.)

The authors are with the Center for Power Electronics Systems,
Virginia Polytechnic Institute and State University, Blacksburg, VA
24061 USA (e-mail:, mohamed4@vt.edu; feichao@vt.edu; fclee@vt.
edu; lqvt@vt.edu).

Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2019.2896082

Fig. 1. Data centers distribution system: (a) traditional ac distribution;
(b) dc distribution with 48 V bus.

systems are replaced by a local dc 48 V battery backup [4].
Significant challenges rise with that proposed architecture. The
48 V voltage regulator module (VRM) located in the vicinity
of the CPU has to be designed with very high efficiency and
high power density [5].

A great amount of work has been done with the 48 V VRM
for both data center and telecommunication applications. They
can be categorized as one-stage and two-stage solutions.

A two-stage 48 V VRM is the first commercially avail-
able solution by Vicor [3], [6]. Their soft-switched first-stage
buck-boost preregulator module (PRM), cascaded with a soft-
switched unregulated sine amplitude voltage transformation
module (VTM), enables their solution to achieve high efficiency
and high density. However, the solution is not easily scalable as
designed in high current levels (>100 A/module). Another two-
stage approach was used in [5], [7], and [8], with an unregulated
inductor-inductor-capacitor (LLC) dc–dc transformer (DCX) as
the first stage and a conventional multiphase regulated buck
converter for the second stage. This solution reported a high ef-
ficiency and high density with significant improvement for light
load efficiency. The two-stage architecture was proposed in [4]
and [9], replacing the isolated bus converters with a resonant
switched capacitor circuit that can achieve a high efficiency
of 98.2% and power density of 500 W/in2 for the first stage
converter; however, there is no reported two-stage efficiency or
power density for the 48/1 V conversion. Another state-of-art
product was proposed by STM Microelectronics [10] based on
a single-stage quasi-resonant converter with a current-doubler
rectifier reported in [11] and [12]. The converter can operate with
zero voltage switching (ZVS) in all loading conditions with a
high efficiency of 93%. However, the topology requires four
magnetic components, reducing the converter power density. In

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 193

Fig. 2. Sigma converter structure.

[13]–[15] a current-tripler 48 V VRM with a compact mag-
netic structure was proposed, together with a 1-MHz self-driven
scheme that solves the problem of synchronous rectifier (SR)
switching and can achieve very high efficiency at high-frequency
operation. However, in the proposed scheme not all the primary
side switches can achieve ZVS at light load, resulting in a sig-
nificant efficiency drop during light loading conditions.

The Sigma converter concept was first proposed in [16] and
[17], for 12 V VRMs that exhibited outstanding performance
over multiphase buck converters. The same architecture was
later used in different applications [18], [19] demonstrating a
very efficient operation. In this paper, the same concept was
revisited and proposed for a single-stage 48 V VRM [20]. The
Sigma converter is a quasi-parallel converter that connects two
converters in series from the input side, and in parallel from
the output side. One of the converters is an unregulated isolated
DCX that conducts the bulk power, while the other is a non-
isolated converter responsible for regulating the output voltage
(D2D), as shown in Fig. 2. A potential benefit of this architecture
is its ability to achieve higher conversion efficiency.

Further efforts should be made for the design of the DCX
and D2D to maximize the benefits of this power architecture.
The soft switching properties of the LLC converter enables
operation at a very high frequency to achieve high density while
achieving high efficiency, making it a suitable candidate for this
converter’s DCX. Integrating magnetics with PCB winding and
matrix transformer with the opportunity of flux cancellation has
been reported [21]–[27] to reduce the size and losses of the LLC
DCX transformer at high-frequency operation.

None of the preceding work has discussed the Sigma con-
verter design with integrated magnetics even though the matrix
transformer structure and design will impact the performance of
this converter significantly as will be discussed in the following
sections. In this paper, a detailed design guideline for the Sigma
converter with integrated magnetics will be discussed by which
the right matrix transformer structure can be chosen for differ-
ent input/output voltage variations to maximize the benefits of
this conversion system. A novel matrix transformer which inte-
grates four elemental transformers into one core structure with
printed circuit board (PCB) windings is proposed to achieve
high efficiency and power density. Accompanying the DCX is
a buck converter with PCB winding inductor to realize all the
stringent requirements for regulation dynamics while increasing
the power density.

TABLE I
PROPOSED CONVERTER SPECIFICATIONS AND LLC-DCX TURNS RATIO

DESIGN RANGE

This paper is organized as follows. Section II presents the
design principle of the Sigma converter architecture with inte-
grated magnetics. Section III discusses the optimal design of the
LLC-DCX with a PCB winding matrix transformer. Section IV
optimizes the design of the buck converter with a PCB wind-
ing inductor. Section V presents the converter prototype and the
experimental results. Section VI concludes this paper.

II. DESIGN GUIDELINE OF SIGMA CONVERTER WITH
INTEGRATED MAGNETICS

In the Sigma architecture, both converters have the same input
current, thus, the power sharing between them is proportional to
the input voltage across each of them as in (1). In the proposed
architecture, the DCX converter is an LLC converter operating
at resonant frequency, utilizing the matrix transformer’s leak-
age inductance to form the resonant tank with the addition of
resonant capacitor. The small leakage inductance of the matrix
transformer will result in a large Ln = Lm /Lr resulting in a
constant gain LLC converter that does not change much with
frequency variation. As a result, the input voltage of the DCX
will be the output voltage of the converter multiplied by the
DCX turns ratio n and the remaining voltage will appear on the
buck-D2D as given in (2). The DCX turns ratio n has a signifi-
cant role in the voltage distribution across these two converters
and consequently, the power sharing among them. For efficient
power conversion, the LLC-DCX is required to handle most of
the power as it can be designed with very high efficiency com-
pared to the buck-D2D; the condition VDCX � VD 2D should
be satisfied in order to achieve that goal.

The Sigma architecture has two main design constraints—
the first constraint is to achieve high efficiency of operation
by limiting the maximum allowable voltage appearing on the
buck converter during all operating conditions, this constraint
limits the minimum allowable turns ratio as given in (3). The
second constraint is to ensure a positive voltage across the buck
converter that is always higher than the maximum output voltage
by which the duty ratio is always (D < 1) and this condition
is given by (4) and sets the maximum allowable turns ratio.
Vinm in , Vinm ax , Vom in , Vom ax are the maximum and minimum
input and output voltages, respectively, Dm ax is the maximum
buck duty ratio, and Vbuckm ax is the maximum stress on the
buck converter.

Different applications will require a specific design of this
architecture based on the constraints mentioned above. The pro-
posed converter specifications and the turns ratio design range
are listed in Table I. The maximum allowable voltage across
the buck converter is set to be Vbuckm ax < 30 V , this will allow

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194 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 3. (a) Basic matrix transformer structure with multiple elemental
transformer. (b) Primary winding implementation with PCB winding.

using low voltage devices for the buck converter to maximize
its efficiency and maintain the bulk power to flow through the
LLC-DCX in all operating conditions

PDCX /PD 2D = VDCX /VD 2D (1)

VDCX = nVo VD 2D = Vin − nVo (2)

nm in >
Vinm ax − Vbuckm ax

Vom in
(3)

nm ax <
Vinm in
Vom ax

− 1
Dm ax

. (4)

Although the maximum turns ratio (nm ax = 43) will result in
the most efficient operation, the implementation of specific turns
ratio with matrix transformer is constrained by other limiting
factors. First, the matrix transformer with core simplification and
integration by the flux cancellation method has been proposed
in [21] and [25] by which two elemental transformers can be
integrated using a single UI-core, resulting in significant core
loss and footprint reduction. This means that we always need
an even number of elemental transformers (2, 4, 6, . . . , etc.)
in order to take the advantage of flux cancellation and core
integration for high efficiency and power density.

Second, the basic structure of matrix transformer with
multiple elemental transformers is shown in Fig. 3(a), where
the single transformer is divided into multiple elemental
transformers connected in series from the primary side and
in parallel from the output side. To ensure equal current
sharing between these elemental transformers, the number
of turns in each elemental transformer should be equal, i.e.,
(nTR1 = nTR2 = . . . = nTRN ). Third, with the requirement
of multiple turns per elemental transformer (nTRx > 1), these
turns should be implemented in more than one layer in order
to have an entrance and exit path for the primary side current
without using extra via or PCB layers as shown in Fig. 3(b).
Finally, the number of primary turns per PCB layer should be
equal in order to maintain a balanced magnetomotive force
(MMF) across the transformer winding and ensure perfectly
interleaved primary and secondary windings to reduce all
ac-related winding loss.

Applying these four PCB winding implementation related
constraints to the design specifications and architecture
constraints listed in Table I will result in all the design options

TABLE II
LLC-DCX WITH MATRIX TRANSFORMER OPTIONS FOR SIGMA CONVERTER

WITH DIFFERENT PRIMARY SIDE CONFIGURATIONS

Fig. 4. Proposed 48/1 V-80 A Sigma converter structure.

listed in Table II, where, NE is the number of elemental trans-
formers, nTR is the turns ratio of each elemental transformer,
and ntotal = NE × nTR is the LLC-DCX total transformer
ratio.

It is clear that different matrix transformer and primary side
configurations will have different impact on the Sigma converter
operation, the first and last options NE = 4 and NE = 10 will
result in the highest possible converter efficiency with the high-
est power flowing through the LLC-DCX. Although both have
the same impact on the architecture, for simplicity of the design,
the first option (NE = 4 )was chosen for this design, the case
with NE = 10 can be a possible candidate if a higher current
converter is required. Although half bridge (HB) configuration
have lower turns ratio, it requires more PCB layers compared to
the full bridge (FB) configuration to implement the PCB wind-
ing, so FB was selected to reduce the cost and complexity of the
proposed converter. The proposed Sigma converter structure is
shown in Fig. 4, the total DCX turns ratio is n = 40 : 1. The
benefits of this design can be shown from the power-sharing
graph in Fig. 5. At most operating conditions, the LLC-DCX
handles most of the output power by which higher overall ef-
ficiency is expected. The same design guidelines can be used
for other 48 V VRMs with different input and output voltage
and power requirements to select the optimal matrix transformer
structure for each application. The optimization of this matrix
transformer will be discussed in the following section to achieve
the highest possible efficiency and power density.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 195

Fig. 5. Power sharing between the LLC-DCX and the buck-D2D.

III. LLC CONVERTER WITH MATRIX TRANSFORMER DESIGN
AND OPTIMIZATION

The design of LLC-DCX for high output current and low
output voltages is very challenging. The necessity of paralleling
multiple SRs to handle this high output current results in cur-
rent sharing problems and large transformer termination losses,
a practice that should be avoided if possible. The concept of the
matrix transformer is to employ various elemental transformer
arrays interwired to form a single transformer. This will re-
duce the total transformer losses by splitting the current among
various elemental transformers and in the same time achiev-
ing flux cancellation wherever possible. The matrix transformer
has exhibited an outstanding performance when used in various
applications. In addition to minimizing termination losses, the
simple PCB winding implementation makes it suitable for this
application, where high output current of the LLC-DCX is re-
quired. In this section, the design and optimization of the matrix
transformer for the LLC-DCX will be discussed in detail.

A. Integration of LLC-DCX Matrix Transformer Structure
and PCB Winding Implementation

For the proposed Sigma converter, the LLC-DCX requires
a transformer with (40:1) turns ratio. This single transformer
was broken into four elemental transformer arrays as shown
in Fig. 6, where the transformer leakage and magnetizing in-
ductances with an additional capacitor are used to form the
resonant tank of the LLC-DCX. The primary windings of this
structure are connected in series while the secondary windings
are connected in parallel. Hence, there would be no current shar-
ing problem between paralleled secondary windings or SRs. To
further reduce conduction losses, the proposed structure par-
allels only two SRs at each secondary winding. Transformer
termination is the physical connection between the transformer
windings and the corresponding primary and secondary devices.
They contribute to a large portion of the transformer losses when
operating at high switching frequencies [21]. The matrix trans-
former structure helps split the output current among different
transformer outputs, thus reducing conduction and termination
losses significantly.

Fig. 6. Proposed LLC-DCX with matrix transformer.

A potential drawback of the matrix transformer approach is
the increased footprint and core loss due to the increased number
of magnetic cores. By operating at very high switching frequen-
cies, the magnetic core size can be reduced. To achieve high
power density, the complex four-transformer structure shown
must be simplified. Originally, the four elemental transformers
each utilize a separate UI-core as shown in Fig. 7(a). By rear-
ranging the four transformers in a way that two transformers
are on the top side (TR1 and TR2) and two on the bottom side
(TR3 and TR4) we can integrate the four transformers with one
core structure with a wide center leg as the return flux path of
each elemental transformer as in Fig. 7(b). By reversing the cur-
rent direction in TR3 and TR4, the flux in the wide center leg
will be in opposite directions and cancel each other, reducing
the total core loss and allowing the removal of this center leg
without scarifying any winding or core loss. Hence, the four
transformers can be integrated into one core structure with four
transformer pillars, which can be easily manufactured, saving a
significant amount of space and core loss as shown in Fig. 7(c).
The proposed integration method not only helps with the reduc-
tion of the core loss and footprint but also helps in achieving a
perfectly current sharing between all the transformer secondary
windings. Integrating the four transformers into a single core
structure helps achieve a symmetrical air gap for all the four el-
emental transformers. Although the four primary windings are
connected in series, each elemental transformer will see a differ-
ent magnetizing inductance determined by its own air gap; any
asymmetry in the magnetizing inductances between these ele-
mental transformers will create a current unbalance between the
secondary windings as well. With the single core structure, the
tolerance in these air gaps can be well-controlled to avoid these
problems when compared to using two single UI-cores [25].

The proposed matrix converter is implemented with a 14-layer
PCB and 2 oz copper for each layer. The detailed PCB winding
arrangement is shown in Fig. 8, the yellow arrows indicate the
current directions in the positive half-cycle. Layers 1 and 14 are

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196 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 7. Derivation of proposed matrix transformer: (a) original four ele-
mental transformer structure with separate UI-cores; (b) rearranged four
elemental transformers integrated in one core with a wide center leg;
and (c) integrated matrix transformers with one core structure without
center leg.

used to place the SRs and the output capacitors. Each set of paral-
lel SRs have one device on Layer 1 and the other device on Layer
14. These devices and capacitors are then connected to the cor-
responding secondary winding through vias. This arrangement
helps reduce the termination connections between windings and
SRs, while splitting the termination current into two layers. This
reduces termination losses significantly. Layers 3 and 6 are one
set of primary windings. In each layer, five turns are wrapped
around each core pillar and then both layers are connected in se-
ries, totaling the required 40 turns. A parallel connection is made
with Layers 9 and 12, which is another set of primary windings
to reduce conduction losses. The remaining layers are for the
center-tap secondary windings. Each layer has one turn, and all
layers are in parallel, to reduce conduction losses. The primary
and secondary windings are perfectly interleaved to reduce the
ac losses due to the proximity effect as shown in Fig. 8(b).

B. Matrix Transformer Design Optimization

To optimize the matrix transformer design, the tradeoff be-
tween total transformer losses and the footprint is evaluated, and
then the optimal switching frequency is selected. First, the im-

Fig. 8. PCB winding arrangement of the proposed matrix transformer:
(a) Layers 1&14 for SRs and output capacitors. (b) 14 layer PCB
arrangement. (c) Layers 3 and 9 for primary#1 windings. (d) Layers 6 and
12 for primary#2 windings. (e) Layers 2, 5, 8, and 11 for secondary#1
windings. (f) Layers 4, 7, 10, and 13 for secondary#2 windings.

TABLE III
CORE SHAPE IMPACT ON WINDING LOSS

pact of the core pillar shape on the winding losses was evaluated.
A rectangular core versus a circular core pillar was evaluated
by finite-element analysis (FEA) simulations; both cases have
the same core area and winding width. The results in Table III
show a 16–22% winding loss reduction with the circular post
due to the shorter current path length. Secondly, various high
frequency magnetic materials were previously surveyed in [5]
and the results showed that the ML-91 from Hitachi shows the
lowest core loss density for this high-frequency operation and
therefore, it was selected for the proposed LLC-DCX converter.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 197

Fig. 9. Transformer total losses and footprint at 1.5 MHz and full load.

Fig. 10. Transformer losses variation with switching frequency.
(a) Winding loss. (b) Core loss.

The design optimization of matrix transformer has been dis-
cussed in previous literature [23]–[25] for 400/12 V converters,
the total transformer loss is calculated at the optimal footprint
and then a design point is selected as a tradeoff between effi-
ciency and power density. The same design methodology was
used for this transformer by adding a new design parameter,
which is the operating switching frequency; the total trans-
former losses versus optimal footprint at full load and nominal
voltage conditions at 1.5 MHz switching frequency are shown
in Fig. 9. Due to the low output voltage and high frequency, the
volt·second applied on the core is very small, and the winding
losses are more dominant with very small core losses.

With lower switching frequencies, the ac related winding
loss will reduce, while the core loss increases due to the higher
volt·second as shown in Fig. 10. From the results in Fig. 11,
the total losses are highest at high switching frequencies, when
reducing the frequency, a reduction in the total losses occurs
until 1 MHz is reached. This is because the reduction in the
winding losses is counteracted by a significant increase in the
core losses, so further reducing the switching frequency will
result in a higher total transformer loss.

To achieve high efficiency and power density, the design re-
gion is highlighted in Fig. 11. The corresponding total loss vari-
ation with different switching frequencies was plotted as shown
in Fig. 12. With different footprints, the total losses tend to have
a minimum loss point at 1 MHz switching frequency; therefore,
1 MHz was selected as the operating frequency. The efficiency
of the converter was then calculated, and the final design point

Fig. 11. Transformer total loss versus footprint at different switching
frequencies.

Fig. 12. Transformer total losses versus switching frequency.

Fig. 13. Transformer fringing flux impact. (a) Cross-sectional view of
fringing flux distribution. (b) Current distribution in Layer 1. (c) Current
distribution in Layer 14.

was selected at a footprint of 300 mm2, since after that point,
the increase in the converter efficiency is marginal.

The magnetizing inductance of the transformer is created by
adding an air gap between the core pillar and the magnetic plate.
A great amount of fringing flux will spread through the air gap
creating many eddy current losses in the nearby layers. This
could be severe for the designed transformer. The fringing flux
at the air gap was simulated using ANSYS Maxwell and the
results shown in Fig. 13 show the strong fringing flux at the air
gap of one of the four elemental transformers. Layer 14, which
is closer to the air gap, handles the same amount of current,
but has ten times more losses than Layer 1. This is due to the

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198 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 14. Total transformer losses versus extending the core air gap.

TABLE IV
PARALLEL LAYER CURRENT DISTRIBUTION

strong fringing flux. To solve this issue, the air gap needs to
be pushed away from the PCB layers by a distance hf r . Using
FEA simulation, different hf r values were evaluated, and the
results are shown in Fig. 14. The total loss reduced significantly
with the higher hf r , until reaching a diminishing return point at
hf r = 0.6 mm, which was chosen in the final design.

In the proposed PCB winding arrangement shown in Fig. 8(b),
we have two primary parallel layers and four secondary winding
parallel layers. Although we minimized the losses due to the
fringing flux, it tends to attract the current to the layers close
to the transformer air gap resulting in an unbalanced current
sharing as listed in Table IV. This issue has not been addressed
in this paper and more analysis needs to be done in order to have
perfect current sharing between layers.

IV. BUCK CONVERTER DESIGN OPTIMIZATION WITH PCB
WINDING INDUCTOR

The Sigma converter was designed so that most of the power
flows through the higher efficiency LLC-DCX while the buck
converter is responsible for regulating the output voltage. From
Fig. 5, it is clear that the power and voltage applied to the buck
converter is variable, depending on the operating condition. In
the worst case (Vo = 0.8 V and Vin = 55 V), the buck con-
verter will experience a voltage stress of (Vbuckm ax = 23 V)
and should handle a current of about (33 A), so devices with a
minimum voltage rating of 40 V are required for the buck con-
verter. Low voltage gallium nitride (GaN) devices have shown
an outstanding performance compared with silicon devices. In
this design, the high side switch is EPC2015c while the low
voltage switch is EPC2024. An optimal layout presented in [28]
was used for the layout of the discrete GaN devices to minimize
the effect of parasitic inductances and their effect on switching
related losses. The inductor design for this buck converter is

Fig. 15. Proposed single-turn PCB winding inductor structure: (a) top
view and (b) cross sectional view.

Fig. 16. Measured efficiency of buck converter with discrete inductor
and PCB winding inductor.

important to achieve high power density and high efficiency.
For low voltage buck converters, the common practice is using
a commercial discrete inductor that has a very low dc resistance
(DCR) and low core loss. However, these inductors have a large
footprint and high profile, which reduces the overall converter
power density significantly.

In this proposed Sigma converter, the LLC-DCX uses a
14-layer PCB to implement the DCX transformer. The same
PCB can be utilized to implement a single-turn inductor. As the
PCB copper thickness is smaller than the copper foil thickness
used by discrete inductors, the inductor windings can be parallel
connected in multiple layers, to reduce the total inductor DCR.
The basic structure of the proposed PCB winding inductor is
shown in Fig. 15. An EI-core shape with ML-95 material from
Hitachi was used to implement the single-turn inductor. An in-
ductance of L = 190 nH and a DCR of RDC = 0.53 mΩ are
achieved. Although the DCR in the proposed design is larger
than the commercial discrete inductors, the efficiency reduc-
tion is negligible since the buck converter is only handling a
small amount of output current. Using this PCB winding induc-
tor will help achieve high power density without scarifying the
efficiency. A buck converter with commercial discrete inductor
and PCB winding inductor was experimentally evaluated. The
measured efficiency shown in Fig. 16 shows that the buck con-
verter with PCB winding inductor has higher efficiency in most
operating regions.

The reason for this is the lower core loss of the designed PCB
winding inductor; the ac-related loss of the PCB winding in-
ductor was evaluated using ANSYS Maxwell. The commercial
inductor used is from Würth Elektronik, and the ac-related loss
of this inductor was calculated based on the inductor loss cal-
culator software REDEXPERT. It can be shown from Table V
that the ac-related losses of the PCB winding inductor is three
times lower than that of the commercial inductor. These losses

Electrical Engineering homework help

48 V-to-1 V Transformerless Stacked Active Bridge
Converters with Merged Regulation Stage

Jianglin Zhu, and Dragan Maksimovic
Colorado Power Electronics Center

Department of Electrical, Computer and Energy Engineering
University of Colorado, Boulder, Colorado 80309

Email: jianglin.zhu@colorado.edu

ABSTRACT

Transformerless stacked active bridge (TSAB) convert-
ers are hybrid converters derived from switched capacitor
converters by addition of small inductors. TSAB converters
achieve the highest efficiency around a nominal conversion
ratio because of “soft” charging/discharging of all flying
capacitors, low rms currents and zero-voltage-switching of
power switches. This paper introduces new configurations
of TSAB converters with inductive filter as opposed to ca-
pacitive filter at the output port, which opens opportunities
to merge a regulation stage at the output. The approach
is applied to 48 V to 1 V point-of-load (PoL) conversion
by merging a 6-to-1 Dickson TSAB with a multi-phase
buck converter at the regulation stage, greatly reduced the
need for a bulky intermediate bus capacitor. Experimental
results are provided for a 48 V-to-1 V, 100 A prototype
consisting of a 6-to-1 TSAB operating at 100-125 kHz
using 120 nH inductors, and an off-the-shelf four-phase
buck regulating stage operating at 500 kHz. The prototype
has 91.5% peak efficiency at 25 A and greater than 85%
efficiency up to 90 A.

I. INTRODUCTION

Motivated by the reduction in distribution losses, there is an
increased interest in higher voltage, e.g. Vbus = 48 V, dc dis-
tribution in data center applications, which in turn highlights
the need for high step-down point-of-load (POL) conversion,
e.g. 48-to-1 V, power xPU’s (GPUs, CPUs, and TPUs) on
server boards. In a conventional design, a two-stage ap-
proach is adopted, with an intermediate bus voltage VIB (e.g.
VIB = 12 V), where the output stage is typically implemented
using readily available multi-phase buck regulators. Various
approaches have been pursued to improve the performance
of the front-end Vbus-to-VIB stage, including switched-tank
converters [1], [2], LLC converters [3], resonant SC converter
[4], and TSAB converters [5]. To further improve the power
density and efficiency performance, direct Vbus = 48 V to PoL
converter topologies have also been investigated, such as the
Sigma converter [6], and the DIHC hybrid converter [7], [8].

 

Vbus

c1

c2

c1

c2

 

c2

c1

c1

c2

vIB

C3

C5

C1

L4C4

L2C2

 

Vout

 

c2s

c1s

iIB

vQ9

vQ1
 

Lb1

Lbn

 

Vbus

c1

c2

c1

c2

 

c2

c1

c1

c2

vIB

C3

C5

C1

L4C4

L2C2

 

Vout

 

c2s

c1s

iIB

vQ9

vQ1
 

Lb1

Lbn

 

Lf

Cf

(b)

(a)

Q1

Q2Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q1

Q2Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Fig. 1: Inductive-output 6-to-1 TSAB merged with a multi-phase buck
regulation stage: (a) with a small LC filter in between, and (b) with no
filter in between.

In transformer-isolated converters, core losses and con-
duction losses in the transformer can be significant at high
switching frequency and high turns ratio. Advanced techniques
such as matrix transformer [9], and “integration” of secondary
winding and rectifier [3] have been proposed to address such
challenges. Since galvanic isolation is not required, trans-
formerless solutions, such as hybrid converters, are potentially
advantageous as they offer additional benefits such as reduced
switch voltage stresses, as well as soft switching.

In a two-stage design, the front-end Vbus-to-VIB converter
may be operated as an unregulated “DC transformer” (DCX)978-1-7281-1842-0/19/$31.00 c©2019 IEEE

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VIN

c1

c2

c1

c2

 

c2

c1

c1

c2

vx

L4C4

L2C2

voutLdc

 

VIN

 

vout

(a) (b)

c2s

c1s

C5

C3

C1

C5

C3

C1

C4

C2

Fig. 2: Two 6:1 Dickson TSAB converters: (a) capacitive-output TSAB where
C2, C4 and the output filter capacitor are considered tree branches, and (b)
inductive-output TSAB where the tree branches are C1, C3, C5. The tree
branches are highlighted in bold in the two configurations.

converter with efficiency optimized at a nominal step-down
conversion ratio. A step further has recently been proposed
in [10], [11], where the operation of a front-end switched-
capacitor stage is “merged” with a follow-up buck regulation
stage. Compared with a decoupled two-stage solution, the
front-end and the back-end converters are coupled in oper-
ation so that filter components such as the intermediate bus
capacitors can be reduced or eliminated. A similar approach
is proposed in this paper based on merging a transformerless
stacked active bridge (TSAB) converter and a multi-phase
buck regulator.

TSAB converters [12] are non-isolated hybrid dc-dc con-
verters with characteristics similar to the isolated Dual-Active-
Bridge (DAB) converter [13]. TSAB converters can be de-
rived from switched-capacitor (SC) converters by addition
of small ac inductors to eliminate “hard” capacitor charg-
ing/discharging losses [12]. The operation and control are
similar to the DAB converter [14]: output can be continuously
regulated by simple phase shift control, inductor peak current
are close to minimum and ZVS operation can be achieved
for most of the switches. Compared to other types of hybrid
converters, such as resonant switched-capacitor converters [4],
[15], or switched tank converters [2], [16], [17], which operate
near resonance (fs/fr ≈ 1), TSAB converters are designed to
operate above resonance (fs/fr > 1) with trapezoidal near-
minimum RMS inductor currents, and zero-voltage-switching
of power devices [12]. Above 98.5% efficiency and flat ef-
ficiency curves have been experimentally demonstrated on a
4-to-1 Dickson-based TSAB [5], and a 3-to-1 ladder-based
TSAB converter [18].

Two variants of a merged TSAB/regulation-stage converter
proposed in this paper are shown Fig. 1. The front-end
stage, which is a 6-to-1 Dickson TSAB with an inductive
output filter, is merged with a standard multi-phase buck POL
regulator. The variant in Fig. 1(a) retains a very small LC
filter between the two stages, while the intermediate-bus filter
is completely eliminated in the variant shown in Fig. 1 (b).

The paper is organized as follows: steady-state operation
and soft switching TSAB converters with inductive output port
are described in Section II. An analysis of the merged configu-
rations shown in Fig. 1 is presented in Section III. Design of a
48 V-to-PoL, 100 A prototype is described in Section IV, along
with key experimental results, including operating waveforms
and efficiency curves. The prototype consisting of a 6-to-1
inductive-output Dickson TSAB operating at 100-125 kHz
using 120 nH ac inductors, and an off-the-shelf four-phase
buck regulating stage operating at 500 kHz has 91.5% peak
efficiency at 25 A and greater than 85% efficiency up to 90 A.
Section V concludes the paper.

II. INDUCTIVE-OUTPUT TSAB CONVERTERS

TSAB converters introduced in [5], [12], [18] employ one
or more ac inductors to ensure soft charging and discharging
of flying capacitors. The output port has a dc filter capacitor.
The ac inductors and phase-shift operation yield trapezoidal
current waveforms with low RMS currents, as well as zero
voltage switching. As an example, the 6:1 Dickson TSAB
converter is shown in Fig. 2(a). In this converter, each inductor
shares the output current equally, and switches are operated
with reduced voltage stress (Vout and 2Vout, respectively) and
ZVS is achieved for most of the switches at sufficiently high
load current [5]. In general, capacitive-output TSAB converters
are obtained by inserting ac inductors into the link branches
of the corresponding two-phase switched-capacitor converter.
If the links remain the same in each switched state, hard
charging/discharging loops consisting of capacitors only are
eliminated.

As discussed in [12], the designation of links and tree
branches in an SC converter is not necessarily unique. In the
6:1 Dickson SC converter, if the output branch Vout is treated
as a tree branch, the tree capacitors are C2 and C4 and the
link capacitors are C1, C3, and C5. Inserting ac inductors in
series with the link capacitors yields the 6-to-1 Dickson TSAB
shown in Fig. 2(a). If, however, the output branch Vout is
treated as a link, the link capacitors are C2 and C4, while the
tree capacitors are C1, C3, and C5. Two ac inductors, L2 and
L4 are inserted in series with C2 and C4, respectively, while
a dc filter inductor Ldc is in the output branch, as shown in
Fig. 2(b). It should be noted that the dc filter inductor Ldc
carries the dc output current and ideally does not withstand
any volt-seconds , so that the inductance can be very small, and
inductor losses can be negligible compared to the ac inductors
which carry large ac currents.

A. Steady-state operation

In the inductive-output TSAB of Fig. 2(b), there are four
switched states, as illustrated in Fig. 4. States 1 and 2 are
the power-delivering states, where the inductors withstand
zero volt-seconds; states 1’ and 2’ are the polarity-reversal
states where the ac inductor currents are flipping polarities.
Assuming operation at nominal output voltage, which is the
same as in the original SC converter, the dc filter inductor does
not withstand any volt-seconds, so a very small inductance can

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c1

c2

c1s

c2s

iL2
iL4

IIB/3

iLdc
IIB

Ts

t

j 1 2 11’2′ 2 1’2′

Fig. 3: Ideal operating waveforms in the inductive-output 6:1 Dickson TSAB
converter in Fig. 2(b). c1/c2, c1s/c2s are complementary 50% signals with
phase shift Tϕ. Ideal operation assumes nominal operation above resonance
fs � fr. Dead times are ignored, which is why there is no ripple in the
output filter inductor current iLdc.

(a) State 1′

VIN

C5 VOUT
Ldc

C1

L2C2

C3
L4C4

C3
L2

C2
C1

VOUT
Ldc

C5

L4

C4

VIN

C5 VOUT
Ldc

C1

L2

C2

C3

L4

C4

C3

L2 C2

C1

VOUT
Ldc

L4 C4

C5

(b) State 2′

(c) State 1 (d) State 2

vx
vx

vxvx

Fig. 4: Four switched-states in the inductive-output TSAB of Fig. 2(b). States
1 and 2 are power-delivering states, and states 1’ and 2’ are polarity-reversal
states.

be employed. Trapezoidal ac inductor currents can be realized
by introducing phase shifts between the control signals of the
two legs of the full-bridge rectifier (Q1 − Q4). Four control
signals c1,c2 and c1s, c2s are required, and the corresponding
timing diagram is shown in Fig. 3.

The balanced flying capacitor voltages are:

Vout ≈ VC1 ≈ Vbus − VC5 (1)

By symmetry,
VC3 ≈ Vbus/2 (2)

By volt-seconds balance applied to L2 and L4,

VC2 =
VC1 + VC3

2
(3)

 

VIN

c1

c2

c1

c2

 

c2

c1

c1

c2

C3

C5

C1

L4C4

L2C2

c2s

c1s Q1

Q2
D3

D4

Q5

Q6

D7

Q8

D9

Q10

vout

 

VIN

c1

c2

c1

c2

 

c2

c1

c1

c2

C3

C5

C1

L4C4

L2C2

c2s

c1s Q1

Q2
D3
D4

Q5

D6

Q7

D8

Q9

Q10

voutLdcLdc

(a) (b)

Fig. 5: Zero voltage switching transitions during (a) dead-time before c2 turns
on, and (b) dead-time before c1 turns on.

VC4 =
VC3 + VC5

2
(4)

Similar to the capacitive-output TSAB converter shown in
Fig. 2(a), the average output current is controlled by the phase
shift:

ILdc =
Vbus

8Lacfs
ϕ(1 − ϕ) (5)

where ϕ = 2Tϕ/Ts, and Lac = L2 = L4. Similar to a DAB
converter, operating away from the nominal voltage results
in increased volt-seconds on inductors and consequently in-
creased RMS currents.

B. Zero voltage switching transitions

For the full-bridge switches Q1 − Q4, inductor current of
Ldc forward biases the body diodes of either Q1,Q2 or Q3,Q4
during dead-times, so zero voltage switching can always be
achieved. Fig. 5 illustrates a ZVS transition for top switches
Q6 − Q9: the body diodes of these switches are forward-
biased by the inductor currents during the dead-time, assuming
sufficiently large inductive energy storage, i.e., sufficiently
large load current. Similar analysis shows that for the left of
the switches Q5,Q10, ZVS cannot be achieved. Importantly,
the ZVS switches Q6 − Q9 also block the highest voltage
(2Vout), while the hard switched devices only block Vout.

III. INDUCTIVE-OUTPUT TSAB CONVERTER MERGED
WITH A REGULATION STAGE

This section describes how an inductive-output TSAB con-
verter can be used as a front-end stage in a high step-down
application such as 48 V-to-PoL conversion. The follow-up
PoL converter can be a standard multi-phase buck converter,
as shown in Fig. 1(a). Furthermore, the small intermediate-bus
LC filter can be completely eliminated as shown in Fig. 2(b).
In this variant, the buck inductor serve the function of the
output inductor Ldc.

Eliminating the LC intermediate-bus filter imposes two
constraints. First, higher RMS currents are induced in some of
the TSAB capacitors and switches. The switching frequency of
the buck converter is typically much higher than the switching

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frequency of the TSAB converter. As a result, the buck induc-
tor current flows through C1 and C5 alternatively in states
1 and 2, which increases the RMS currents in capacitors C1
and C5 and the TSAB corresponding switches. The inductor
currents iL2 ad iL4 however, remain essentially unaffected.

Additionally, to ensure balanced voltages in the TSAB
converter, switching frequency ratio between the TSAB and
the buck stages should be an even integer value in the converter
of Fig. 1(b). If a multi-phase buck stage is employed, as
shown in Fig. 1(b), interleaving yields an equivalent switching
frequency proportional to the number of phases. The RMS
currents supplied by C1 and C5 can then be much smaller.

IV. DESIGN AND EXPERIMENTAL RESULTS FOR A
48 V-TO-1 V PROTOTYPE

This section presents the design and the experimental
results for a 48V-to-1 V prototype based on the merged
TSAB/regulation-stage converter shown in Fig. 1.

A. 48V-to-PoL prototype design

The design process for the 6-to-1 TSAB in Fig. 1 is
summarized in this section.

LTM4680

L2 L4

LTM4680

Fig. 6: 48 V-to-PoL/100 A prototype including 6:1 inductive-output TSAB
with planar inductors followed by a four-phase buck regulator. L2,L4 are
plannar inductors with 4 mm in height.

1) Selection of TSAB L and C values: The choice of the
inductive impedance ZL = ωsL and capacitive impedance
ZC = 1/(ωsC) affects the TSAB RMS currents. Let Rp be
the series resistance in the tanks consisting of ac inductors
L2, L4 and link capacitors C2, C4, respectively. Assuming
constant Rp, the quality factor Q =


(ZLZC)/Rp and the

ratio k = fs/fr =

ZL/ZC determine the waveshapes of the

ac inductor currents. As can be seen from simulations, a high
Q (Q > 10) and low k (k < 1.5) result in near-sinusoidal
current waveforms, whereas a low Q (Q < 3) and high k
(k > 1.5) result in near-trapezoidal waveforms. The k and
Q values also affect the required value of the phase shift for
a given output current. A larger phase shift corresponds to a
larger circulating current.

Switches

Q1 − Q4,Q5, Q10 EPC2023

Q6 − Q9 EPC2020

Passive components

C1 48 µF

C3,C5 80 µF

C2,C4 72 µF

L2,L4 120 nH

fsw,tsab 100-125 kHz

fsw,buck 500 kHz

k 1.7

Q ≈ 6

Inductor design

Number of turns 1

Core PC95 ELT11x4

AC resistance 4 mΩ

TABLE I: Parameters in the 48-to-1 V, 100 A prototype

In the prototype design, k = 1.7, Q = 10 and fs = 100 kHz
are selected, which ensures quasi-trapezoidal ac inductor cur-
rents with less than 2% required phase shifts at full load. The
corresponding parameter values are listed in Table I.

2) Design of ac inductors: Two low-profile 120 nH ac
inductors are implemented as planar low-profile inductors
(4 mm in height). The core material is PC95. Low inductances
allows for a single-turn design, which eliminates ac copper
losses due to proximity effects. Since the air gap is on the
opposite side of the PCB winding, the losses due to fringing
field are also relatively small. At the switching frequency, the
ac resistance obtained by finite-element simulation is found
to be very close to the dc resistance. Inductor core losses are
relatively low compared to the copper losses due to the low
peak-to-peak flux density.

3) Loss modeling: Major losses in the TSAB stage include
switch losses (conduction, switching losses), magnetic losses
(ac copper loss and core loss), and capacitor ESR losses.

In this design with four phase interleaved buck follow-up
stage, the RMS currents in the TSAB switches depend on
the nature of the intermediate-bus filter. If a large LC filter
with cutoff frequency lower than twice the TSAB switching
frequency is used, the RMS currents are minimized. On the
other hand, if a small (or no) filter is used, the RMS currents
are increased. In this case, the conduction loss model must
take into account the input current ripple in the follow-up buck
regulation stage.

Regarding switching losses, note that ZVS is achieved for
most of the TSAB switches assuming sufficient load current.
For the hard switching devices, and for the soft switching
devices at light load, switching losses are estimated by taking
into account voltage/current overlap losses and Coss losses.

Inductor copper losses are estimated based on ac resistance
found by finite-element analysis as shown in Table I, while
core losses are estimated using the iGSE method [19],.

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4) Multi-phase buck converter: The multi-phase buck con-
verter used in the prototype is based on two off-the-shelf
LTM4680 components in parallel [20], to obtain a four-phase
configuration with current mode control.

B. Experimental results

A 48 V-to-1 V converter prototype capable of 100 A output
current is shown in Fig. 6, and the component values are listed
in Table I.

Switch node voltages and ac inductor currents in the TSAB
stage in the configuration shown in Fig. 1 (a) are shown in
Fig. 7. Dips in vIB in Fig. 7 is attributed to dead-time between
signal c1/c2 and c1s/c2s. For example. during the dead-time
of Q1/Q2, both switch operate in reverse conduction mode,
and vIB collapses.

vIB(10V/div)

vQ9(12.5V/div)

iL2(5A/div)

iL4(4A/div)

Fig. 7: Waveforms in the TSAB stage with an LC filter: Vbus = 48 V,
VIB = 7.84 V, IIB = 15 A, fs = 100 kHz, time division: 4 µs/div. vQ9
and vIB are as shown in Fig. 1(a).

Efficiencies are measured separately for the TSAB and for
the four-phase buck stage from 10 A to 90 A load current
for Vbus = 48 V, Vout = 1 V as shown in Fig. 8. The
TSAB efficiency remains above 97.5% across the measured
load range with peak efficiency of 98.2% at 40 A. The four-
phase buck stage is operated with the four phases interleaved,
and the peak efficiency is around 94% at 20 A. The resultant
system peak efficiency is 91.5% at 25 A, and drops to
85% at 90 A. A small filter inductor Lf ≈ 60 nH and
filter capacitors Cf ≈ 22µF is used for each buck module.
The peak efficiency is comparable with other 48 V-to-1 V
hybrid converter solutions, such as DIHC [21], and heavy-
load efficiencies are improved. The heavy-load efficiency is
comparable to or slightly higher compared to transformer-
based two stage solutions, such as the current doubler design
reported in [22]. Additionally, compared with other direct
48 V-to-1 V solutions, regulation is much simpler because
readily available off-the-shelf buck modules can be employed.
Estimated loss breakdown in the TSAB stage for 1 V/40 A
output is shown in Fig. 9. The load current of the TSAB stage
is around 5 A, with longer than minimum dead times required
to achieve ZVS. In the model, the switch conduction losses
includes Rds,on losses as well as losses due to the PCB trace
resistances, and reverse-conduction losses are related to the
voltage drops across GaN FETs during dead-times.

As explained in Section III, removing the LC filter in
Fig. 1(b) is advantageous for size reduction. Fig. 10 compares
measured efficiency in the no-filter configuration of Fig. 1(b)

20 40 60 80 100
Output Current [A]

86

88

90

92

94

96

98

100

Buck

System

TSAB

91.5%

E
ff
ic

ie
n
cy

[
%

]

Fig. 8: Measured efficiencies of the 6:1 TSAB stage and the 8:1 four-phase
buck converter. The system efficiency is shown for the configuration in
Fig. 1(a) at 48 V input and 1 V output.

and small LC filter configuration of Fig. 1 (a). The small LC
filter yields improvement in efficiency in this case because the
RMS current in the switches are reduced compared to the case
with no filter. In terms of operation, LC filter is not necessary.
The operating waveforms for no filters are shown in Fig. 11.
Even with no input capacitors, the buck input voltage (vIB)
ripple is less than 1 V. This is because the flying capacitors,
especially C1 and C5 serve as an effective filter for the input
current ripple.

Conduction losses
27%

Switching losses
35%

Reverse-conduction losses
28%

Lac losses
8%

Ldc losses
1%

ESR losses
1%

Fig. 9: Modeled loss breakdown for the 6:1 TSAB prototype with Vbus =
48 V input, 1 V output, at the output current of 40 A.

V. CONCLUSIONS

TSAB converters [5], [12], [18] employ small ac induc-
tors while operating at relatively low switching frequency,
and offer high efficiency at nominal conversion ratio due to
“soft” charging/discharging of all capacitors and zero-voltage-
switching of power devices. TSAB converters can be cascaded
with a standard multi-phase buck regulation stage to construct
48 V-to point-of-load voltage around 1 V for server and

Authorized licensed use limited to: University of Illinois at Chicago Library. Downloaded on January 26,2022 at 20:06:13 UTC from IEEE Xplore. Restrictions apply.

Fig. 10: Measured efficiency for the configuration with a small LC filter
(Lf =60 nH, Cf = 8µF ) in Fig. 1 (a) and the no-filter configuration in
Fig. 1(b). Operating conditions: Vbus = 40 V, Vout = 1 V, fs,T SAB =
125 kHz, fs,buck = 500 kHz.

vQ9(12.5V/div)

Buck switch node
(5V/div)

vIB(1V/div)

iL4(2A/div)

Fig. 11: Experimental waveforms in the no-filter configuration in Fig. 1(b):
Vbus=30 V, Vout = 1 V, Iout = 30 A, fs,T SAB = 125 kHz, fs,buck =
500 kHz. Time division: 2 µs/div. vQ9 and vIB are as shown in Fig. 1(b).

other applications. To further reduce the losses associated with
ac inductors, this paper presents a new configuration of the
TSAB converter with an inductive output which eliminates
one of ac inductors. A follow-up multi-phase buck regulation
stage can be merged with the inductive-output TSAB using a
small LC filter. Completely removing the intermediate filter
is also feasible with a slight trade-off in conduction losses. An
experimental prototype is constructed using a 6-to-1 inductive-
output Dickson TSAB operating at 100-125 kHz followed
by an off-the-shelf four-phase buck regulator operating at
500 kHz. The prototype has 91.5% peak efficiency at 25 A
and greater than 85% efficiency up to 90 A.

ACKNOWLEDGMENT
The authors would like to acknowledge Lockheed Martin

for supporting research reported in this paper.

REFERENCES
[1] Y. Li, X. Lyu, D. Cao, S. Jiang, and C. Nan, “A 98.55% efficiency

switched-tank converter for data center application,” IEEE Transactions
on Industry Applications, 2018.

[2] S. Jiang, S. Saggini, C. Nan, X. Li, C. Chung, and M. Yazdani,
“Switched tank converters,” IEEE Transactions on Power Electronics,
2018.

[3] M. H. Ahmed, A. Nabih, F. C. Lee, and Q. Li, “Low loss integrated
inductor and transformer structure and application in regulated llc
converter for 48v bus converter,” IEEE Journal of Emerging and Selected
Topics in Power Electronics, pp. 1–1, 2019.

[4] Z. Ye, Y. Lei, and R. C. Pilawa-Podgurski, “A resonant switched ca-
pacitor based 4-to-1 bus converter achieving 2180 w/in 3 power density
and 98.9% peak efficiency,” in Applied Power Electronics Conference
and Exposition (APEC), 2018 IEEE. IEEE, 2018, pp. 121–126.

[5] J. Zhu and D. Maksimović, “A family of transformerless stacked
active bridge converters,” in Applied Power Electronics Conference and
Exposition (APEC). IEEE, 2019.

[6] M. Ahmed, C. Fei, F. C. Lee, and Q. Li, “High-efficiency high-power-
density 48/1v sigma converter voltage regulator module,” in 2017 IEEE
Applied Power Electronics Conference and Exposition (APEC), March
2017, pp. 2207–2212.

[7] G. Seo, R. Das, and H. Le, “Dual inductor hybrid converter for point-
of-load voltage regulator modules,” IEEE Transactions on Industry
Applications, pp. 1–1, 2019.

[8] ——, “A 95%-efficient 48V-to-1V/10A vrm hybrid converter using
interleaved dual inductors,” in 2018 IEEE Energy Conversion Congress
and Exposition (ECCE), 2018, pp. 3825–3830.

[9] M. H. Ahmed, C. Fei, F. C. Lee, and Q. Li, “48-v voltage regulator
module with pcb winding matrix transformer for future data centers,”
IEEE Transactions on Industrial Electronics, vol. 64, no. 12, pp. 9302–
9310, 2017.

[10] J. Baek, P. Wang, S. Jiang, and M. Chen, “Lego-pol: A 93.1% 54v-1.5v
300a merged-two-stage hybrid converter with a linear extendable group
operated point-of-load (lego-pol) architecture,” in 2019 20th Workshop
on Control and Modeling for Power Electronics (COMPEL), June 2019,
pp. 1–8.

[11] J. Baek, P. Wang, Y. Elasser, Y. Chen, S. Jiang, and M. Chen, “Lego-
pol: A 48V-1.5V 300A merged-two-stage hybrid converter for ultra-
high-current microprocessors,” in 2020 IEEE Applied Power Electronics
Conference and Exposition (APEC), 2020, pp. 490–497.

[12] J. Zhu, R. Schuess, and D. Maksimovic, “General properties and syn-
thesis of transformerless stacked active bridge converters,” in 2019 20th
Workshop on Control and Modeling for Power Electronics (COMPEL),
June 2019, pp. 1–6.

[13] R. W. De Doncker, D. M. Divan, and M. H. Kheraluwala, “A three-
phase soft-switched high-power-density dc/dc converter for high-power
applications,” IEEE transactions on industry applications, vol. 27, no. 1,
pp. 63–73, 1991.

[14] J. Zhu and D. Maksimović, “Dynamic modeling of a hybrid switched-
capacitor-based converter with phase-shift control,” in 2018 IEEE 19th
Workshop on Control and Modeling for Power Electronics (COMPEL),
June 2018, pp. 1–6.

[15] S. R. Pasternak, M. H. Kiani, J. S. Rentmeister, and J. T.
Stauth, “Modelling and Performance Limits of Switched-Capacitor
DC-DC Converters Capable of Resonant Operation with a Single
Inductor,” IEEE Journal of Emerging and Selected Topics in Power
Electronics, vol. 6777, no. c, pp. 1–1, 2017. [Online]. Available:
http://ieeexplore.ieee.org/document/7987696/

[16] S. Jiang, S. Saggini, C. Nan, and X. Li, “Switched Tank Converters,”
IEEE Transactions on Power Electronics, vol. 34, no. 6, pp. 5048–5062,
2019.

[17] Y. He, S. Jiang, and C. Nan, “Switched tank converter based partial
power architecture for voltage regulation applications,” in Applied Power
Electronics Conference and Exposition (APEC), 2018 IEEE. IEEE,
2018, pp. 91–97.

[18] J. Zhu, R. Scheuss, and D. Maksimovic, “Ladder transformerless stacked
active bridge converters,” in 2019 IEEE Energy Conversion Congress
and Exposition (ECCE), Sep. 2019, pp. 151–156.

[19] K. Venkatachalam, C. R. Sullivan, T. Abdallah, and H. Tacca, “Accurate
prediction of ferrite core loss with nonsimisoidal waveforms using only
steinmetz parameters,” Proceedings of the IEEE Workshop on Computers
in Power Electronics, COMPEL, vol. 2002-Janua, no. June, pp. 36–41,
2002.

[20] “Dual 30A or single 60A module regulator with digital power system
management,” Available at https://www.analog.com/media/en/technical-
documentation/data-sheets/LTM4680.pdf (2020/09/30).

[21] R. Das, G. Seo, and H. Le, “Analysis of dual-inductor hybrid converters
for extreme conversion ratios,” IEEE Journal of Emerging and Selected
Topics in Power Electronics, pp. 1–1, 2020.

[22] “Lmg5200 gan 48v to 1v point of load evaluation module,” Available
at https://www.ti.com/tool/LMG5200POLEVM-10 (2020/09/30).

Authorized licensed use limited to: University of Illinois at Chicago Library. Downloaded on January 26,2022 at 20:06:13 UTC from IEEE Xplore. Restrictions apply.

Electrical Engineering homework help

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 1

A P P L I C AT I O N N OT E : A N 0 0 6 E P C 1 0 0 1 , E P C 1 0 0 7

A 48 VDC to 1 VDC converter using conventional
silicon-based power MOSFETS is usually realized
in two stages; a preliminary stage that converts
the input voltage to a 12 V intermediate voltage,
and a point of load (POL) converter that performs
the second stage conversion from the intermedi-
ate voltage to the required 1 V output. This dual-
stage technique is required since a single stage
48 V to 1 V converter will need to operate at a
small duty cycle of about 2%. At high frequencies
(250 kHz and above) the pulse widths required to
operate the converter fall below 100 nsec which
is prohibitively short for Silicon based MOSFETs.
EPC1001(100 V, 5.6 mΩ) and EPC1007 (100 V, 24
mW) GaN-on-silicon transistors have been shown
to operate at pulse widths well below 100 ns.
Turn-on and turn-off times of about 4 ns are
achieved using an industry standard pin driver.

EPC1001 and EPC1007 Parameter Overview

The EPC1001 and EPC1007 enhancement mode
Gallium Nitride power transistors are the first
of a new generation of devices that go beyond
the limitations of Silicon technology. Whereas
similar voltages and RDS(on) can be found in sili-
con power MOSFETs, the typical gate charge
required for switching EPC1001 and EPC1007
devices, 11 nC and 2.7 nC respectively, com-
bined with this voltage and RDS(on) is well beyond
silicon’s reach. Table 1 compares the capability
of these two devices with the benchmark de-
vices on the market today. As can be seen, the
product of RDS(on) and Gate Charge (RDS(on) x QG
product) is six times better than the best perfor-
mance achieved in silicon.

In addition to the superior RDS(on) x QG product,
EPC’s GaN transistors have an integrated re-
verse diode with a VF of about 2 V and no reverse
recovery charge.

EPC1001 and EPC1007 transistors are available
as bumped “flip-chip” devices. Because of the in-
novative Gallium-Nitride-on-Silicon technology
used by EPC, the substrate is isolated from the
active device area by at least 300 V (This parame-
ter is being characterized and may be revised at
a future date). This affords an additional oppor-
tunity for power density improvements com-
pared with packaged Silicon transistors as the
device can be directly connected to a heatsink
without an intermediate insulating layer.

Single-Stage 48 V – 1 V DC-DC Conversion
Simplifies Power Distribution While
Significantly Boosting Conversion Efficiency

Edgar Abdoulin and Alex Lidow, Ph.D.

Efficient Power Conversion Corporation’s (EPC) hyper fast Gallium Nitride (GaN) power tran-
sistors offer performance enhancements well beyond the realm of silicon-based MOSFETs.
Standard power converter topologies can greatly benefit from the added performance and
leap to areas not attainable with current MOSFET designs; improving converter efficiency,
while maintaining the simplicity of converter designs.

Table 1 – Comparison Between EPC1001/EPC1007
GaN Transistors and Silicon Benchmark Devices

In Brief
A first-generation buck converter that delivers
high efficiency while converting from 48 V to
1 VDC has been designed and characterized. The
use of enhancement mode, Gallium Nitride
power transistors from EPC has made this
practical for the first time.

• New generation of power transistors
outperforms silicon in high frequency
switching applications by a wide margin

• Promises to open many new doors to
applications previously dominated by
power MOSFETs.

• EPC is planning a rapid set of introductions
through 2009 and 2010 to cover a broad
spectrum of power applications:

– Isolated and non-isolated
DC-DC conversion

– Synchronous rectification
– Class-D Audio
– Motion control
– Cell phones and base stations

Manufacturer Part Number Voltage RDS(on) max QG max (RDS(on) x QG)

IR IRLB4030

100

4.5 130 585

IR IRLSL4030 4.5 130 585

Fairchild FDP054N10 5.5 203 1117

IPP050N10LG 6.4 163 1043

Fairchild FDMS86101 8.0 55 440

IPD068N10N3G 12.3 68 836

IR IRLR3110ZPbF 14.0 48 672

BSC159N10LSFG 21.5 35 753

Fairchild FDMC86102 24.0 18 432

BSC205N10LS 28.0 41 1148

Vishay SUD06N 10-225L 225.0 3 608

EPC EPC1001
100

7 11 77

EPC EPC1007 30 2.7 81

EFFICIENT POWER CONVERSION

A P P L I C AT I O N N OT E : A N 0 0 6

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 2

S i n g l e – s t a g e 4 8 V- 1 V D C – D C Co nve r te r

EPC1001 and EPC1007 Gate Characteristics

The equivalent circuit of the gate characteristics
of the GaN power transistor is depicted in Fig 1.
The gate consists of a small resistor (RG ~ 0.5 Ω),
and a Capacitor, QG, with a breakdown above 6
VDC. Full enhancement of the device channel is
achieved by 5 VGS and it is important to maintain
a gate drive level that will not exceed the 6 VDC
absolute maximum. The EPC1001 required QG to
turn on is only about 10 nC and EPC1007 requires
about 2.7 nC.

Gate Driver Considerations.

Due to the hyper-fast switching characteristics
of the GaN power transistors, high dV/dt’s are
present when the device switches from one
state to another. These high dV/dt’s can cause
high currents to flow in the miller capacitor
(CGD). In a half bridge topology a small driver
with a relatively high RDS(on) could cause an
undesired turn-on of the lower device when
the actual requirement is to keep the device
off. This phenomenon will increase the risk of
shoot-thru currents and result in excessive loss-
es. Therefore, the selection of a proper driver is
not only driven by the current/switching time
requirement, but also by the need to provide
a low impedance path for stray currents gener-
ated by the high dV/dt’s.

As an example, with a CGD of ~100 pF and a dV/
dt of 12 V/ns, the current injected in the driver
equates to about 1.2 A. Since the minimum
threshold of the EPC1001 is 0.7 V, the RDS(on)
needed to avoid turning the lower device on is:

Driver

High Current
in Driver

High dV/dt
on Drain

5 V

CGD

GaN

Fig 2 – High dV/dt can cause high currents to flow in the gate driver.

RG

QG

Gate

Source

Fig 1 – EPC1001 and EPC1007 Gate Structure

RDS(on) (Driver) < 0.7 V/1.2 A = 0.58 Ω

CH1: Lower Gate | CH2: Lower Device VDS | dV/dt ~ 12 V/nsec

Fig 3 – Half Bridge Topology with high gate drive RDS(on) – High dV/dt causes “Bump” in Lower gate drive.

A P P L I C AT I O N N OT E : A N 0 0 6

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 3

S i n g l e – s t a g e 4 8 V- 1 V D C – D C Co nve r te r

EPC1001/EPC1007 Evaluation Circuit

The EPC1001/EPC1007 evaluation circuit is a
non-isolated “buck” converter capable of oper-
ating with up to 72 VDC input, while generating
0.5 to 3.5 VDC output at up to 15 A. A function
generator is required to set the PWM pulses for
various output voltages and current combina-
tions. Dead time adjustments are accomplished
by two on-board potentiometers to optimize
performance vs. various dead time settings.
The EPC transistors are covered by a detachable
heat sink. Due to the internal body diode of the
EPC1001, an external re-circulating diode is not
necessary.

Fig 4a – Schematic of EPC1001/EPC1007 Evaluation Circuit

Fig 4b– Schematic of EPC1001/EPC1007 – Dead time generator

A P P L I C AT I O N N OT E : A N 0 0 6

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 4

S i n g l e – s t a g e 4 8 V- 1 V D C – D C Co nve r te r

Table 4 – 48 VDC to 1 VDC conversion

f(kHz) VIN (V) IIN (mA) VOUT (V) IOUT (A)

200

48

252.5 1.001

10.006

82.64

300 258.8 1.005 80.95

400 264.7 1.007 79.30

500 270.3 1.006 77.58

Table 5 – 24 VDC to 1 VDC conversion

f(kHz) VIN (V) IIN (mA) VOUT (V) IOUT(A)

200

23.97

484.7 1.007

10.006

86.73

300 488.1 1.007 86.12

400 492.0 1.006 85.35

500 497.4 1.007 84.51

EPC1001/ EPC1007 Evaluation
Circuit Performance

Typical performance data for the EPC1001/
EPC1007 evaluation circuit has been measured
over a range of input voltages, output cur-
rents and operating frequencies. Tables 2 and
3, as well as Fig 5, show efficiencies at 24 VDC
and 48 VDC to 1 VDC conversion from 2 A to 12 A.
All measurements were performed at 250 kHz
switching frequency.

100

95

90

85

80

75

70
0 2 4 6 8 10 12 14

y (
%

)

IOUT (ADC)

Conver y vs Output Current (f=250 KHz)

24 VDC to 1 VDC

48 VDC to 1 VDC

Fig 5 – Converter efficiency vs. input voltage and output current

Table 2 – 48 VDC to 1 VDC conversion

f(kHz) VIN (V) IIN (mA) VOUT (V) IOUT(A)

250

48.06 54.8 1.004 2.0053 76.44

48.05 126.2 1.004 5.0066 82.89

48.05 203.8 1.005 8.0079 82.18

48.04 258.5 1.004 10.006 80.90

48.03 318 1.005 12.008 79.01

Table 3 – 24 VDC to 1 VDC conversion

f(kHz) VIN (V) IIN (mA) VOUT (V) IOUT(A)

250

24.02 92.58 1.007 2.0053 90.81

24 231.6 1.006 5.0066 90.61

23.97 380.6 1.003 8.0079 88.04

23.97 483.6 1.002 10.006 86.49

23.96 598.3 1.005 12.008 84.18

100

95

90

85

80

75

70
100 200 300 400 500 600

y
(%

)

Frequency (kHz)

y vs Switching Frequency (VOUT =1 VDC, IOUT=10 ADC)

24 VDC to 1 VDC

48 VDC to 1 VDC

Fig 6 – Converter efficiency vs. switching frequency.

Tables 4 and 5 and Fig 6 depict operation of the
converter at 24 and 48 VDC inputs over a range
of operating frequencies.

A P P L I C AT I O N N OT E : A N 0 0 6

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 5

S i n g l e – s t a g e 4 8 V- 1 V D C – D C Co nve r te r

Fig. 7 shows the loss distribution in the con-
verter for both 24 V and 48 V inputs operating
at 250 kHz. Top and bottom device losses in-
clude conduction as well as switching losses.
Other losses include PCB resistive losses, out-
put capacitor ESR, and parasitic losses due to
skin effects and layer to layer capacitances.

Top Device Losses
Bottom Device Losses
Inductor Losses
Other

Loss Distribution

Top Device Losses
Bottom Device Losses
Inductor Losses
Other

Loss Distribution

Fig 7 – Distribution of losses in the EPC1001/EPC1007 Evaluation Board (48 or 24 VDC(IN), 1 V/10 AOUT )

Typical Operating Waveforms

Typical waveforms obtained during actual
operation are shown in Fig’s 8 thru 11.
Measurements were performed at 250 kHz
operating frequency.

Fig 8 – Overall converter operation (48 VIN, 1 V and 10 AOUT ) – 250 kHz

Fig 9 – Low side device gate drive and drain voltage (48 VIN, 1 V and 10 AOUT ) Fig 10 – Top device turn on/off (48 VIN, 1 V and 10 AOUT )

A P P L I C AT I O N N OT E : A N 0 0 6

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 6

S i n g l e – s t a g e 4 8 V- 1 V D C – D C Co nve r te r

Fig 11 – Top device turn on and turn off times (48 VIN, 1 V and 10 AOUT)

Conclusions

A first-generation buck converter that delivers high efficiency while converting from 48 VDC to 1 VDC
has been designed and characterized. The use of enhancement mode, Gallium Nitride power transis-
tors from EPC has made this practical for the first time.

This new generation of power transistors outperforms silicon in high frequency switching applica-
tions by a wide margin and promises to open many new doors to applications previously dominated
by power MOSFETs.

EPC is planning a rapid set of introductions through 2009 and 2010 to cover a broad spectrum of
power applications including isolated and non-isolated DC-DC conversion, synchronous rectification,
Class-D Audio, motion control, cell phones, and base stations.

Electrical Engineering homework help

Final Exam, ECE 448- Spring 2022, UIC Name:

Page 1 of 4

Final Exam, ECE 448 Transistors – Spring 2022
University of Illinois at Chicago

10:30 am to 12:30 pm on May 03, 2022

Name: UIN:

[30 points] PROBLEM # 1
Assume a hypothetical pn junction with the doping profile shown below, derive the
expression for the depletion width and the electric field under equilibrium conditions (Note
“a” is negative)

Final Exam, ECE 448- Spring 2022, UIC Name:

Page 2 of 4

[30 points] PROBLEM # 2
In a silicon MOS capacitor with an n-type substrate and a p + polysilicon gate (Ef = Ev),
the substrate doping is uniform with Nd = 2 × 1018 cm−3. The oxide thickness is 3 nm. There
is a p + channel contact biased at -1V relative to the substrate. The voltage drop across the
oxide is Vox = −0.6 V.
(a) Determine the state of the channel region (accumulation, flat-band, depletion, strong
inversion, etc.).
(b) Determine the applied gate voltage.
(c) Sketch the charge density, electric field and energy band diagram for the system.

Final Exam, ECE 448- Spring 2022, UIC Name:

Page 3 of 4

[20 points] PROBLEM # 3
Calculate the base transit time in a npn transistor with NDE= 1019 cm-3, NAB = 1017 cm-3, VBE=
0.8V and a neutral basewidth W = 0.8 μm. Assume DnB= 18 cm2 s-1 and independent of position.

Final Exam, ECE 448- Spring 2022, UIC Name:

Page 4 of 4

[20 points] PROBLEM # 4
List the steps needed for fabricating an n-MOSFET device. Draw figures to illustrate your
response clearly.

Electrical Engineering homework help

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
80%

82%

84%

86%

88%

90%

92%

94%

D001

Vin = 48 V @ 400 kHz
Vin = 48 V @ 600 kHz
Vin = 48 V @ 800 kHz
Vin = 48 V @ 1 MHz

Q1

Vin C1

LMG5200

Q2

* *

C2

T1

ISO7420 TPS53632

UCC27512

VFB

Q3

Q4

L2

L1

CO RL

SGND

Vout0.8 V ~ 1.2 V / 40 A

Copyright © 2016, Texas Instruments Incorporated

1TIDUC72A – September 2016 – Revised September 2016
Submit Documentation Feedback

Copyright © 2016, Texas Instruments Incorporated

LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

TI Designs
LMG5200: 48 to 1 V or 40 A Single-Stage Converter
Reference Design

All trademarks are the property of their respective owners.

Description
The PMP4497 is a gallium nitride (GaN) based
solution for 1.0-V and 40-A core, field programmable
array (FPGA), and application specific integrated
circuit (ASIC) applications. With high integration and
low switching loss, the GaN module LMG5200 enables
a high-efficiency, single stage from the 48 to 1.0 V
solution to replace the traditional two-stage solution.
This design shows the GaN performance and the
system advantages compared with the 2-stages
solution. A low-cost ER18 planar printed circuit board
(PCB) transformer is embedded on the board. The
design was achieved in a compact form factor (45 mm
× 26 mm × 11 mm). The size could be further reduced
by optimizing frequency and components. A design
guide with complete test data is provided to facilitate
new designs.

Resources

PMP4497 Design Folder
LMG5200 Product Folder
TPS53632 Product Folder
ISO7420FE Product Folder
UCC27512DRSR Product Folder
TLV70450DBVR Product Folder
TLV70433DBVR Product Folder
PMP4435 Tools Folder

ASK Our E2E Experts

Features
• Input Voltage From 36 to 60 V
• Single Stage Half-Bridge and Current Doubler
• Peak Efficiency up to 93.7% at 48 V, 1.0 V, and

600 kHz
• LMG5200 GaN FET Module
• DCAP+ Control With the TPS53632
• 400-kHz to 1-MHz Operation Frequency
• I²C Configurable From 0.8 to 1.2 V
• Optional Resistor-Configurable Load-Line
• Output Over Voltage Protection (OVP), Overcurrent

Protection (OCP), and Output Under Voltage
Protection (UVP)

Applications
• Servers and High-Performance Computing
• Telecom DC-DC Module
• Industrial Board Computer, Field Programmable

Gate Array (FPGA), and Application Specific
Integrated Circuit (ASIC)

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.

System Overview www.ti.com

2 TIDUC72A – September 2016 – Revised September 2016
Submit Documentation Feedback

Copyright © 2016, Texas Instruments Incorporated

LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

1 System Overview

1.1 System Description
The PMP4497 implements the 48- to 1-V single-stage power conversion using a hard-switching half-
bridge converter with the current-doubler synchronize rectifier. Figure 1 shows the topology implemented
in this board. A LMG5200 and EPC2023 GaN FETs are used on the primary side and secondary side
respectively. With the GaN MOSFET advantages, such as the zero-reverse recovery, low capacitance,
and low Rds-on, the converter could achieve a smaller size and a higher efficiency compared with a
traditional two-stage solution (for example, an eighth brick and the 12-V POL module).

Because the half-bridge converter is transformer-based, the converter can be isolated. The TPS53632
controller can support an isolated converter by using a digital isolator, for example, the ISO7420, to drive
the primary-side LMG5200. The PMP4497 supports input voltage from 36 to 60 V and output voltage from
0.8 to 1.2 V; the default output voltage is 1.0 V. The output current supports up to 40 A; fan cooling is
recommended to help dissipate the heat when operating above 20 A. The output voltage is programmable
through an I²C interface. See the TPS53632 data sheet (SLUSBW8) for the details of the I²C program
command and the data format.

1.2 Key System Specifications

Table 1. Key System Specifications

PARAMETER TEST CONDITIONS MINIMUM TYP MAXIMUM UNIT
INPUT AND OUTPUT CHARACTERISTICS

Input voltage
range 36 48 60 V

Input current VIN= 36 V, VOUT= 1.2 V, IOUT= 40 A — — 1.4 A
Output voltage I²C programmable 0.8 1.0 1.2 V
Output voltage

tolerance IOUT= 0A — — 10 mV

Output current — — — 40 A
Over-current

protection — — 60 A

SYSTEM CHARACTERISTICS
Switching
frequency 400 600 1000 kHz

Peak efficiency VIN= 48 V, VOUT= 1.0 V, IOUT= 15 A, @600kHz withoutcontroller and driver losses — 92.9 — %

Full-load
efficiency

VIN= 48 V, VOUT= 1.0 V, IOUT= 40 A, at 600kHz without
controller and driver losses — 89.9 — %

Transient load
voltage variation

Transient at the 25% full load (10 A), the ELoad slew
rate is 2.5 A/µs — ±3 — %

6

4

LMG45200

UVLO

UVLO and
Clamp

Level
Shifter

5

8

3

1

2

9

7

VCC

HI

LI

HB

VIN

HS

SW

PGND

AGND

Copyright © 2016, Texas Instruments Incorporated

Q1

Vin C1

LMG5200

Q2

* *

C2

T1

ISO7420 TPS53632

UCC27512

VFB

Q3

Q4

L2

L1

CO RL

SGND

Vout0.8 V ~ 1.2 V / 40 A

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

1.3 Block Diagram

Figure 1. PMP4497 Block Diagram

1.4 Highlighted Products

1.4.1 LMG5200
The LMG5200 device integrates an enhancement-mode GaN FET half-bridge power stage with a 100-V
driver, which provides a compact solution.

The device extends the advantages of discrete GaN FETs by offering a more user-friendly interface. The
device is an ideal solution for the applications requiring high-frequency and high-efficiency operation in a
small form factor. Integration reduces the board clearance and creepage needed for a discrete solution
while minimizing the loop inductances to ensure fast switching and low ringing.

Figure 2. LMG5200 Functional Block Diagram

ADDR

OSR/USR

USR

OSR

ISUM

DROOP

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1.4.2 TPS53632
The TPS53632 device is a driverless step-down controller with I²C control. Its advanced features, such as
D-CAP+ architecture, provide fast transient response, and high-efficiency operation with minimized output
capacitance. The TPS53632 device supports the standard I²C revision 3.0 interface for dynamic control of
the output voltage and current monitor telemetry. The device also has dynamic phase adding and
shedding control and is able to enter single-phase, discontinuous-current mode operation to maximize
light-load efficiency.

Figure 3. TPS53632 Functional Block Diagram

1.4.3 ISO7420
The ISO7420 is a low-power, dual-channel digital isolator. The device is used in the design to deliver
isolated control signals from the secondary side to the LMG5200 on the primary side. The ISO7420
provides galvanic isolation up to 2500 V RMS for 1 minute per UL and 4242 VPK per VDE. This device
has two isolated channels. Each channel has a logic input and output buffer separated by an insulation
barrier. Used in conjunction with an isolated power supply, the device prevents noise current from entering
the local ground and interfering with or damaging sensitive circuitry.

1

2

3

4

5

6

VDD

200 N��

230 N��

UVLO

VDD

VDD

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1

2

3

4

8

7

6

5

VCC1

INA

INB

GND1

VCC2

OUTA

OUTB

GND2

Is
o

la
tio

n

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 4. ISO7420 Block Diagram

1.4.4 UCC27512
The UCC27512 is a single-channel, high speed, low-side gate-driver device. The device can effectively
drive the MOSFET and insulated gate bipolar translator (IGBT) power switches with 4-A peak source and
8-A peak sink asymmetrical drive capability. Using TI intellectual property (IP) that inherently minimizes
shoot-through current, the UCC27512 is capable of sourcing and sinking high peak-current pulses into
capacitive loads and offering rail-to-rail drive capability with small propagation delay, typically 13 ns. In the
PMP4497 design, a duty signal to IN- of the driver to drive the synchronous rectifier MOSFET. IN+ is
bypassed by connecting it to VDD directly.

Figure 5. UCC27512 Block Diagram

t0 t1 t2 t3 t4 t5

t

t

t

t

t

Vgs_Q1

Vgs_Q2

t

iL1

iL2

iO

Io/2

VNP_T1

Io/2

Io

+Vin/2

-Vin/2

TSTS/2

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

2 System Design Theory
Benefitting from the output ripple current cancellation technique, a half-bridge converter with a current
doubler rectifier circuit is suitable for low-profile, high-voltage input and large output current applications
and provides higher efficiency. The converter key theoretical waveforms are shown in Figure 6.

Figure 6. Half-Bridge with Current Doubler Timing Diagram

* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t3 ~ t4

SGND

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* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t2 ~ t3

SGND

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* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t1 ~ t2

SGND

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* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t0 ~ t1

SGND

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2.1 Operation Modes of the Converter With Current Flow
The converter in the continuous current mode (CCM) mode has four operation modes during one full
switching period as shown in Figure 7.

Figure 7. Operation Modes With Current Flow

O S

in P

V N
M D

V 2 N
= = ´

´

( )0 S 0 S
Vin NS

V D T V 1 D T
2 NP

æ ö
´ – ´ ´ = ´ – ´ç ÷

è ø

( )0 S
1

1

V 1 D T
i

L

´ – ´
D =

( )00 V-

Sin
0

P

NV
V

2 N

æ ö
´ -ç ÷

è ø

2
0 2

di
0 V L

dt
– = ´

1
0 1

di
0 V L

dt
– = ´

Sin 2
0 2

P

NV di
V L

2 N dt
´ – = ´

1
0 1

di
0 V L

dt
– = ´

2
0 2

di
0 V L

dt
– = ´

1
0 1

di
0 V L

dt
– = ´

2
0 2

di
0 V L

dt
– = ´

Sin 1
O 1

P

NV di
V L

2 N dt
´ – = ´

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

2.2 Circuit Operation and Description
Time interval t0 → t1:
During the t0 → t1, Q1 and Q4 are on, and Q2 and Q3 are off. The transformer T1 secondary winding begins
to charge the output inductor L1, and the L2 is discharged to the output capacitor and the load.

Time interval t1 →t2:
During the t1 → t2, Q1 and Q2 are off, and Q3 and Q4 are on. Both L1 and L2 discharges the current to the
output; the inductor current is discharged linearly.

Time interval t2 →t3:
During the t2 → t3, Q1 and Q4 are off, and Q2 and Q3 are on. The transformer T1 secondary winding
inverses the polarity and begins to charge the output inductor L2, and the current in L1 is discharged to the
output capacitor and the load.

Time interval t3 →t4:
During the t3 → t4, Q1 and Q2 are off, and Q3 and Q4 are on. Both the L1 and L2 are discharged to the
output; the inductor current is decreased linearly.

According to the simplified operation models, during the t0 → t1 (DTs) the winding begins to charge the

inductor L1 with the voltage , and the current i1 increases linearly. Within the t1 → t4 (1-D), the
current i1 decreases with the voltage . The inductors ripple current is as follows:

Based on the voltage-second balance of the inductor, the CCM voltage transfer ratio is

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

3 Getting Started Hardware

3.1 Hardware
The converter output range is from 0.8 to 1.2 V, and the input voltage range is from 36 to 60 V. Operation
should be within the input/output voltage ranges.

If the converter shuts off due to UVP or OCP, the controller IC must be rested to re-enable the converter.
To change the output voltage, the I²C bus should be used to set the TPS53632. Consult the user guide for
the TPS53632 for the necessary VID protocol (SNVU520). The TPS53632 controller’s switching
frequency, voltage ramp rate, load line, and OCP could be changed by modifying resistor values on the
board. The TPS53632 data sheet (SLUSCJ3) includes the detailed procedures to choose these
components.

3.1.1 Test Equipment
• DC voltage source: supplies the EVM from 36 V to 60 V, output current >2A
• DC bias source: 6 to approximately 9V or 0.5 A, two outputs for the primary and secondary
• Oscilloscope: >200-MHz operation, use oscilloscope probes with a pigtail spring ground clip instead of

the standard alligator clip
• DC multimeter: capable of 100-V measurement, suitable for efficiency
• DC load: supports 1-V operation at up to 50 A in current-mode operation
• Fan cooling: 200-LFM minimum airflow is recommended to cool the PCB when operating over 20-A

output current

3.1.2 Measurement Procedure
The following procedure is used to measure the board.
1. Connect the input and output supplies as shown in Figure 8.
2. Connect the oscilloscope to the board to measure input/output voltage. Use a bayonet nut connector

(BNC) to a subminiature version A (SMA) cable or differential probe for the noise immunity.
3. Connect the bias supply. The onboard LDO provides 5 and 3.3 V to the power and control circuitry.
4. Power up the input supply. Operation below 36 V may result in the output voltage range out of

regulation.
5. Power up the bias supply to start the converter. The output voltage will ramp up and the output voltage

should be in regulation.
6. Enable the electronic load and set to a desired load current.
7. Test and measure the input/output voltage response, efficiency, and so forth.

3.1.3 Shutdown Procedure
After the measurements have been completed, shut down the board by the following steps:
1. Disable the input voltage supply.
2. Disable the electronic load.
3. Disable the bias supply.

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4 Testing and Results

4.1 Test Setup

Figure 8. Connection Points

Figure 9. Testing Setup With Full Load

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 10. Oscilloscope Probe Connections

Input Voltage (V)

P
o
w

e
r

L
o
ss

(
W

)

34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

D003

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
84%

86%

88%

90%

92%

94%

D002

Vin = 36 V
Vin = 48 V
Vin = 60 V

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
80%

82%

84%

86%

88%

90%

92%

94%

D001

Vin = 48 V @ 400 kHz
Vin = 48 V @ 600 kHz
Vin = 48 V @ 800 kHz
Vin = 48 V @ 1 MHz

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2 Test Data
The following sections detail the typical performance curves and waveforms of the PMP4497.

4.2.1 Efficiency
Note that most of the efficiency results in this section do not include the controller losses (aside from
Figure 14). The default output voltage is 1.0 V.

Figure 11. Efficiency Curve Without Controller Loss Versus Switching Frequency

Figure 12. Efficiency Curve Without Controller Loss Versus Output Current

Figure 13. Power Loss (No Load) Versus Input Voltage

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
80%

82%

84%

86%

88%

90%

92%

94%

D005

Vin = 48 V @ 0.8 V 600 kHz
Vin = 48 V @ 1.0 V 600 kHz
Vin = 48 V @ 1.2 V 600 kHz

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
78%

80%

82%

84%

86%

88%

90%

92%

D004

Vin = 36 V
Vin = 48 V
Vin = 60 V

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 14. Efficiency Curve with Controller Loss Versus Output Current

Figure 15. Efficiency Curve without Controller Loss Versus Vout Change (Through I²C)

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2.2 Transient Load Waveforms

Transient load (0 to 25%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (25 to 50%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (50 to 75%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (75 to 100%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (10 to 90%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (0 to 100%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2.3 Switching Node Waveforms (Full Bandwidth)

Primary Vsw versus PWM1_P no load
C1: Vsw switching node 10 V/Div
C2: PWM1_P driver signal 2.0 V/Div

Primary Vsw versus PWM1_P full load
C1: Vsw switching node 10 V/Div
C2: PWM1_P driver signal 2.0 V/Div

Primary Vsw versus PWM1_P full load
C1: Vsw switching node 20 V/Div
C2: PWM1_P driver signal 5.0 V/Div

Primary Vsw versus PWM1_P full load
C1: Vsw switching node 20 V/Div
C2: PWM1_P driver signal 5.0 V/Div

Secondary Vds_Q3 versus Vgs_Q3 at 40 A
C1: Vds_Q3 5.0 V/Div
C2: Vgs_Q3 5.0 V/Div

Secondary Vds_Q3 versus Vgs_Q3 at 40 A
C1: Vds_Q3 5.0 V/Div
C2: Vgs_Q3 5.0 V/Div

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2.4 IR Scan Thermal Gradient (With Fan Cooling)

Figure 16. 48-V Input at Full Load (1.0 V and 40 A)

LMG5200

VIN Capacitors

Multi-Layer PCB

Small Return Path
Minimizes Power Loop

Impedance

xxx
xxx

SW

VIN

PGND

Metal 3

PGND

Legend

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

5 Design Files

5.1 Schematics
To download the schematics, see the design files at PMP4497.

5.2 Bill of Materials
To download the bill of materials (BOM), see the design files at PMP4497.

5.3 PCB Layout Recommendations
High-switching speed is important in a high-efficiency design. Optimizing the PCB layout to minimize the
power loop impedance and parasitic inductance is a necessary measure to achieve the goal.

It is recommended to use a multilayer board. Power loop parasitic impedance should be minimized by
having the input capacitor return path (between VIN and PGND) directly underneath the first layer as
shown in the below Figure 17. Loop inductance is reduced due to inductance cancellation as the return
current is directly underneath and flowing in the opposite direction. The VCC capacitors and the bootstrap
capacitors are placed in the first layer and should be as close to the device as possible.

The AGND of LMG5200 should not be directly connected to PGND in order to avoid the PGND noise and
not to cause spurious switching events due to noise coupling to HI and LI signals. Reducing the
impedance and the inductances on the board and the PCB layout should comply with the clearance and
creepage distance requirements.

Figure 17. Multilayer Board Cross Section With Return Path Directly Underneath for Power Loop

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 18. LMG5200 Top Layer Placement

5.3.1 Layout Prints
To download the layer plots, see the design files at PMP4497.

5.4 Altium Project
To download the Altium project files, see the design files at PMP4497.

5.5 Gerber Files
To download the Gerber files, see the design files at PMP4497.

5.6 Assembly Drawings
To download the assembly drawings, see

Electrical Engineering homework help

A Regulated 48V-to-1V/100A 90.9%-Efficient
Hybrid Converter for POL Applications in Data

Centers and Telecommunication Systems
Ratul Das and Hanh-Phuc Le

Department of Electrical, Computer and Energy Engineering
University of Colorado, Boulder, Colorado

{ratul.das, hanhphuc}@colorado.edu

Abstract—This paper describes the topology, fundamental
operations, and key characteristics of a Dual-Phase Multi-
Inductor Hybrid (DP-MIH) Converter for Point of Load (POL)
telecommunication and data center applications. The circuit
topology employs a unique configuration of switched inductor
and capacitor pairs to achieve complete soft charging and native
voltage balancing of flying capacitors regardless of mismatches
and variations in capacitor and inductor values. The converter
topology and its operation are verified by a five-level DP-MIH
converter prototype capable of delivering maximum load of 100A
at 1V-5V regulated output voltages from a 48V input supply. It
achieves 90.9% peak efficiency and 440 w/in3 power density for
48V-to-1V conversion and 95.3% and 2200W/in3 for a 48V-to-5V
conversion.

Index Terms—Hybrid converter, complete soft-charging,
switched capacitor network.

I. INTRODUCTION

Monthly global mobile data traffic is expected to surpass
100 ExaBytes (EB) in 2023 from around 20 EB today, and
merely ~2 EB in 2013[1]. This exponential growth has put
a critical pressure on the telecommunication infrastructure,
particularly on the architecture of power supply and distribu-
tion for this massive need. The most challenging components
in the power distribution for telecom power delivery include
the point-of-load (POL) converters connected to the 48V
intermediate bus as shown in Fig. 1[2]. In designing 48-
V PoL converters, transformer-based topologies have been a
popular choice with ones that have achieved a good range of
efficiencies around ~90%[3] and up to 93.4% [4]. However,
to maintain this efficiency range these converters either use
a complicated control scheme or have a limited conversion
ratio range[5]. In addition, bulky transformers are not desir-
able for converters that require both high power density and
large conversion ratios in applications where isolation is not
necessary.

Considering stringent space and load constraints, non-
isolated hybrid DC-DC converter topologies have shown
promising results. Notable examples include the 48V-to-1V
converter reported in [6] aiming at high efficiency and high
power density and the 120V-to-0.9V converter in [7] demon-
strating extremely large direct conversion ratios. Employing
a dual-inductor hybrid (DIH) converter architecture, both
converters demonstrated high efficiencies in a moderate load

85-265 V
AC

~400V
DC

DC/DC
48V Intermediate Bus

POL
Conv.

POL
Conv.

3.3V 2.5V

POL
Conv.

1.xVTelecom Unit

~400V
DC

PSU

DC/DC
48V Intermediate Bus

POL
Conv.

POL
Conv.

3.3V 2.5V

POL
Conv.

1.xVTelecom Unit

~400V
DC

PSU

H
ig

h
-V

o
lta

g
e

B
u

s

AC/DC

DC Storage

Fig. 1. Telecom power distribution system with 48V POL converters

S5

S2

Vin

B

A

B

C0 ILoad

S1 A
C1

Vout

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

A

A

B

B

Fig. 2. Dual-Phase Multi-Inductor Hybrid (DP-MIH) Converter

range up to 20A. However, the need for a precise capaci-
tor sizing strategy in [7] or a split phase operation in [6]
creates undesirable design complexities that would in turn
limit performance at heavier loads. Related works preceding
these implementations include the Flying Capacitor Multi
Level (FCML) converter reported in [8], the Hybrid Dickson
converter in [9], [10], and the multiphase series capacitor
Buck converter in [11], [12]. These interesting approaches for
non-isolated POL converters still have various short-comings.
Particularly, the FCML converter needs a capacitor voltage
balancing circuit, the Hybrid Dickson converter requires a
split-phase control and published implementations of the series
capacitor Buck converter exhibits efficiency limited to ~90%

978-1-5386-8330-9/19/$31.00 ©2019 IEEE 1997

S5

S2

Vin

B

A

B

C0 ILoad

S1 A
C1

Vout

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

A

A

B

B

AB1

AB2

(a) State 1(Phase A)

S5

S2

Vin

B

A

B

S1 A
C1

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

C0 ILoad

Vout

A

A

B

B

BB1

BB2

(b) State 3 (Phase B)

S5

S2

Vin

B

A

B

S1 A
C1

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

C0 ILoad

Vout

A

A

B

B

(c) States 2 and 4

Fig. 3. Operating states of the DP-MIH converter

for a conventional 12V-to-1V conversion. The need for higher
efficiency is perhaps self-evident, but larger conversion ratio,
low output voltage, and extremely high output current are also
critical since they are directly related to the space overhead,
thermal managementand hence cost of the input bus distribu-
tion, and to enabling technology scaling of the load process.

In order to explore the boundaries of hybrid converter capa-
bilities, in this paper we introduce, analyze and demonstrate
a Dual-Phase Multi-Inductor Hybrid (DP-MIH) converter),
shown in Fig. 2. The DP-MIH converter is derived as a
continuation of work from the Dual Inductor Hybrid (DIH)
converters [7], [6], and leverages similarities to the series
capacitor Buck converter. Section II describes the converter
operation and key characteristics, including complete soft-
charging operations of all flying capacitors without any spe-
cific capacitor sizing or split phase control, inherent capability
of providing less voltage stress across switches and inductors,
and the benefits of natively balanced inductor currents. Section
IV presents experimental results that validate advantageous
characteristics in enabling a DP-MIH converter converter
prototype to support large conversation ratios from a 48V
input to 1V-5V output at a maximum current of 100 A, and a
maximum load of 500W. Section V concludes the paper.

II. OPERATION OF THE DP-MIH CONVERTER

The paper focuses on a four-level version of the DP-MIH
converter, ignoring the zero level. It is called a 4-to-1 DP-
MIH converter where four is the number of voltage divisions
created by the switched capacitor network. The converter
circuit is shown in Fig. 2. The converter employs three flying
capacitors, four output inductors, and eight switches. As shown
in Figs. 3 and 4, the converter is operated with 4 switching
states within a switching cycle TS where States 1 and 3
are also named energizing phases A and B, respectively. In
Fig. 3, red color represents the capacitors getting charged
while blue implies discharging. The charged inductors in Fig.
3 have the correspondingly matching color in the inductor

current waveforms of Fig. 4. The first three inductors and
flying capacitors form three inductor-capacitor pairs where
each capacitor Ci is directly connected to and soft-charged
by inductor Li in a charging phase, A or B. The last inductor
L4 only handles soft discharging for the capacitor C3. The
capacitors are open-circuited and inactive during States 2 and
4. Every inductor is charged in one energizing phase, A or B,
and discharges to the output during the other energizing phase
and in States 2 and 4. The converter operation converges to
a steady state as each capacitor gets equivalent charge and
discharge once in every cycle, leading to native capacitor
voltage balance and inductor current balance. Charge for each
capacitor comes from either input voltage source for C1 or
from a capacitor at an immediate higher level in case of

A B

iL1(t) iL2(t)

A

D D D D D

B A B
2 3 4 1 2 3 4 1 2 3 4

∆”#

∆”#

∆”#

1

VC2(t)

∆$%

∆”&'(

VC1(t)

∆$%
iL3(t) iL4(t)

TS

1State

D

Phase

vout(t)

)&'(
*

+”$,
*

-“$,
*
“$,
*

)&'(
*

VC3(t)

Fig. 4. Operational waveforms of the DP-MIH converter

1998

TABLE I
SWITCHING NODE VOLTAGES IN ENERGIZING STATES

Switching node voltages
State 1 (Phase A)

Switching node voltages
State 3 (Phase B)

Start End Start End
V x1(AB1)

Vin
4

+ 4VC
2

Vin
6

� 4VC
2

V x2(BB1)
Vin
4

+ 4VC Vin6 � 4VC
V x3(AB2)

Vin
4

+ 4VC Vin6 � 4VC V x4(BB2)
Vin
4

+ 4VC
2

Vin
6

� 4VC
2

C2 and C3. In other words, flying capacitors discharge to
their immediate lower-level capacitors and inductors except for
C3, which discharges directly to L4. Assuming small voltage
ripples in the capacitors and inductor volt-second balance, the
steady-state voltages for C1, C2, and C3 are found as 3Vin4 ,
2Vin
4

, and Vin
4

, respectively.As the result, the four inductors
L1�4 are switched by the same voltage swing of Vin4 at
switching nodes VX1�X4. Each inductor has a charging duty
cycle D, i.e. in Phase A or B, making the output voltage
Vout =

DVin
4

. This intuitive conversion ratio result implies
a straightforward duty cycle control, allowing for a simple
and efficient output voltage regulation. General expressions
for steady-state voltages at the output and across the flying
capacitors for an N-to-1 DP-MIH converter are given as:

Vout =
DVin
N

and VCk =
(N�k)Vin

N
where, k = 1, 2, …., N � 1

(1)

For the intended operation of the converter, while Phases A
and B need to stay non-overlapped, they are not required to
be evenly distributed in the switching cycle. In general, a
uniform distribution of interleaving phases is preferred since it
minimizes the output current and voltage ripples and enables
load transient improvements as similarly found in multi-phase
Buck converters.

III. NATIVE SOFT-CHARGING AND ANALYSIS OF
SWITCHING NODE VOLTAGES

Native Soft-charging Feature

The key reason why this DP-MIH converter converter can
achieve complete soft charging for all flying capacitors is
evident in its operation in which every capacitor is charged
or discharged by an inductor in series. No capacitor is shorted

D
S

P
C

on
ne

ct
io

n

V
ou

t
S

en
se

Output

Input

L2

L4

S1
S5

S2
S3
S4

S6

S7

S8

Remaining circuit components are at the bottom side

C1
C2
C3

Gate Driving
Circuits

2.
49

˝

3.495˝

Fig. 5. A five-level 100-W DP-MIH converter prototype

in parallel with another capacitor or a low impedance source,
and thus no capacitor hard charging. This beneficial soft
charging is achieved natively without any complicated split-
phase control [13], [6] or capacitor sizing strategy [7]. Native
soft charging is also achieved regardless of variations and
mismatches in flying capacitor values that are oftentimes un-
avoidable because of different bias voltages and manufacturing
tolerance.

Analysis of Switching Node Voltages

As described in the operation of the DP-MIH converter
in Section II, all inductors experience an average voltage
swing of Vin

4
and carries an equal average current of Iout

4
.

When charging and discharging the flying capacitors, this
inductor current generates a voltage ripple of 4VC across each
flying capacitor. In other words, the voltage across each flying
capacitor has the same swing of 4VC

2
in addition to its steady-

state average voltage. However, in the operation of converter
shown in Fig. 3, the charging branches, AB1, AB2, BB1, and BB2
in the two phases A and B have different number of capacitors,
i.e. one or two capacitors. Therefore, the voltage swings at the
switching nodes VX1-X4 have different values, as detailed in
Table I. Specifically, during the charging phase VX2 and VX3
experience twice the voltage ripple of VX1 and VX4, leading
to larger variations in the current slope L2 and L3 compared
with L1 and L4 during energizing phase. However, note that
if this 4VC is small compared with Vin4 , the difference in the
inductor currents is insignificant. In addition, regardless of this
small inductor current mismatch 1) each inductor still maintain
a steady periodic waveforms every cycle, and 2) the feature
of native soft-charging for all the flying capacitor described
above is preserved.

IV. EXPERIMENTAL RESULTS
In order to validate the converter operations and advanta-

geous characteristics, a DP-MIH converter prototype depicted

TABLE II
MAJOR COMPONENTS

Components Part information
S1,2,3,4 2xEPC2015c
S5,6,7,8 2xEPC2023
C1 5.8uF 100V TDK
C2 5uF 100V TDK
C3 4.3uF 100V TDK
L1�4 1uH Vishay

Isolators Si8423
Gate Drivers LM5114, LMG1205

1999

TABLE III
COMPARISON CHART

Characteristics DIHC
[6]

Series Capacitor
Buck[11]

DP-MIH converter
(This work)

Input voltage 40-54 V 12 V 48 V
Output voltage 1-2 V 0.6-1 V 1-5 V

Maximum load current 10 A 60 A 100 A
Maximum power 20 W 60 W 500 W
Number of levels 7 5 5

Capacitor sizing and split
phase control

Required Not required Not required

Peak efficiency 93% @ 1V/4A 90.3% @ 1V/15A 90.9% @ 1V/30A

Fig. 6. Measured waveforms of the DP-MIH converter in a 48V-to-2V/15A
conversion

in Fig. 5 was implemented. The key components used in the
design are listed in Table II. Steady-state waveforms of the
four inductor currents, three flying capacitor voltages, and the
output voltage are shown in Fig. 6, verifying the converter
operation as described in Section II. In these experimental
waveforms, the converter was operated at 167-kHz switching
frequency, converting a 48V input to a 2V output and 15A
load. This switching frequency was specifically chosen to cre-
ate large ripples on the flying capacitor voltages and inductor
currents for convenient measurements. The flying capacitor
voltage waveforms in Figure 6 prove that soft charging is
achieved for all flying capacitors while the inductor current
waveforms demonstrates uniform current distribution for all
inductors. To obtain the efficiency in in Fig. 7, the converter
was operated at an optimal switching frequency of 333 kHz

Fig. 7. Measured efficiency of the DP-MIH converter operated at 333 kHz.

for voltage conversions from a 48V input supply to an output
regulated at 1V to 5V with a load current up to 100 A. The
converter achieves peak efficiencies of 90.9% for a 1V/30A
output, 93.6% for 2V/35A and 95.3% for 5V/40A. The ef-
ficiency measurements take into account all the powertrain
components as well as gate driving losses. Considering key
power conversion components, the converter achieves a power
density of 440 W/in3 at 1V and 2200 W/in3 at 5V and a current
density of 440 A/in3.

The DP-MIH converter converter prototype is compared
against previous works in Table III. Compared with the series
capacitor Buck converter [11], this DP-MIH converter con-
verter achieves a similar peak efficienciy for 1-V output while
supporting 4X conversion ratios, i.e. from 48V input instead of
12V, 1.6X maximum current capability, and 2X current at peak
efficiency. Compared with the DIH converter in [6],it achieves
10X maximum output current and 25X output power.

V. CONCLUSION

In this paper, a Dual-Phase Multi-Inductor Hybrid (DP-
MIH) converter was presented with operation analysis and

2000

experimental results. The converter exhibits a superior con-
figuration and performance at higher loads compared with the
state-of-the-art designs because of its unique hybrid topology
configuration and operation that enables complete native soft
charging in all flying capacitors without requiring any complex
control or capacitor sizing method. A 500-W experimental
prototype successfully demonstrates the intended operation
and characteristics, achieving 90.9% peak efficiency for a 48V-
to-1V conversion and regulating an output up to 5 V with loads
up to 100A.

ACKNOWLEDGMENT
This research work received financial and technical supports

from NSF ECCS program award No. 1810470, Oracle, Power
America, Lockheed Martin and the University of Colorado
Boulder.

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http://ieeexplore.ieee.org/document/7041205/

2001

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